High speed USB host mode ISO

[lpcware]

Content originally posted in LPCWare by hannible on Mon Nov 24 02:22:58 MST 2014
Hi,

I am using the NGX 1837 board and looking at the USB host mode implementation for high speed ISO transfer through Lpcusblib.
With reference to ehci.c, can someone help me to understand :

1.   When does the host start to send out IN transactions ?
2.   When does the DMA start ?

There is not much information from the hardware registers description also.


Thanks.

[lpcware]

Content originally posted in LPCWare by hannible on Wed Nov 26 22:45:55 MST 2014
Hi Tsuneo,

Thanks for the concise overview. It is a good start for me.


Best Regards.

[lpcware]

Content originally posted in LPCWare by Tsuneo on Wed Nov 26 08:13:26 MST 2014

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Quote:
There is not much information from the hardware registers description also.

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The USB host controller on LPC1387 follows the EHCI specification.
The manual describes jsut the least information, including the deviation from the spec.
You may download EHCI spec from the Intel site.
http://www.intel.com/content/www/us/en/io/universal-serial-bus/ehci-specification.html
http://www.intel.com/content/www/us/en/io/universal-serial-bus/ehci-specification-for-usb.html

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Quote:
1. When does the host start to send out IN transactions ?

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The outline of the host scheduling of isoc transactions (periodic schedule) are described in "3.1 Periodic Frame List" of the spec.

[img]http://www.lpcware.com/system/files/periodic_schedule.gif[/img]
The host stack binds an isoc transfer descriptor (iTD) to one of the elements of the periodic frame list. At the begining of a frame, the host controller (HC) refers to an element of the list, pointed by the frmae index (FRINDEX), which increments at every frame. HC executes the isoc transaction specified by the iTD, if any, bound to the element of the list. Therefore, the delay (number of frames) is determined by the distance from FRINDEX to the element index to which the iTD is registered. The HC always starts with isoc transfer, if any, in a frame.

In the ehci.c, HcdDataTransfer() calls QueueITDs() for isoc transfer. QueueITDs() accepts a dataBuff of xferLen. This routine splits the dataBuff into shorter buffers of MaxPackageSize (or less). It assignes these buffers to the iTDs starting from the next frame of the current (FrameIdx + FramePeriod). Therefore, the isoc transfer starts at the next (micro-)frame of the current one.

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Quote:
2. When does the DMA start ?

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Received data by the HC is immediately transferred to the registered memory to the iTD, within necessary latency requirements of the HC. When an isoc transaction completes in a (micro-)frame, HC triggers an interrupt at the end of the (micro-)frmae.

Tsuneo