Dual core debug LPC4370 with J-Link problem

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Dual core debug LPC4370 with J-Link problem

1,531件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by ali_asadzadeh on Mon Mar 09 07:05:16 MST 2015
Hi,
I have build a dual core project on LPC4370, But I can not start debugging on Cortex M0 core, j-link complains flash downloading fail! my code is in RAM for cortex M0, here is the M0 project setup,
you can see Keil setup in here,

http://www.imageupload.co.uk/image/5nMS
http://www.imageupload.co.uk/image/5nMU
http://www.imageupload.co.uk/image/5nMa
http://www.imageupload.co.uk/image/5nMN
http://www.imageupload.co.uk/image/5nMs
http://www.imageupload.co.uk/image/5nMu

Do you have any idea what's wrong?
ラベル(1)
0 件の賞賛
返信
6 返答(返信)

1,195件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by ali_asadzadeh on Thu Mar 19 00:37:15 MST 2015
Thanks for the info, I will check that and will update you.
Regards
0 件の賞賛
返信

1,195件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by bavarian on Tue Mar 17 04:36:26 MST 2015
With regards to the debug problem I think the FallGuy was on the right track   8-)

[u]Think about what happens normally at startup with the two cores:[/u]

1. Reset (this can also come from the debugger)
2. Cortex-M4 executes the ROM bootloader
3. Cortex-M4 enters your application code and configures + enables the Cortex-M0
4. Cortex-M0 enters the application code

What does a debugger do? It connects to the debug access port, applies a reset and then gets the core under control.
For the Cortex-M4 this always works fine, because it's started by the hardware. The M0 is in reset until the M4 executes the instruction to let it out of reset. If you don't reach this point, you will not get the M0 core under control.
And what you have set in the debug options for the Cortex-M0 is a "Reset after Connect"!
Most likely the debugger is too fast after the reset and tries to catch the M0 before the M4 let it out of reset. I don't think that you can influence this timing, it's part of the JLink firmware.
Please remove this setting, the debugger will therefore try to connect "silently".

[u]My debug strategy for the Cortex-M0 looks like this:[/u]

1. At the beginning of the M0 code there is a simple wait loop, let's say for 3 seconds
2. I do not check the "Reset after Connect", so the debugger jumps on the chip & core without applying a reset
3. I apply a hardware reset to my board and then start the debugger. The time between these two actions is normally sufficient to get into the wait loop in the M0 code.
4. The debugger catches and stops the Cortex-M0 when it's running in the wait loop.

The same I do if I want to debug both cores at the same time. I insert a wait loop in the M4 code, this guarantees that I catch the M4 before it does anything strange (strange things I have programmed  :)  ). This setup can work with the "Reset after connect". I have two instances of µVision open, the one for the Cortex-M4 catches the M4 and I step through the instruction where the M0 is taken out of reset. Directly after that I start the debugger in the second instance of µVision, which I have prepared to connect to the M0. Then the M0 is catched while it's running in the wait loop. I end up with two debugger and two cores which are stopped. Then I can step through the code.
Consider that all information goes through one interface. The more windows you have open in both debuggers, the more data needs to updated when you do a step or stop at a breakpoint. Take your time when clicking on the step buttons and limit the number of open windows in the GUIs.


[u]With regards to your screenshots, that "Flash download failed":[/u]

If you have no flash specified in your memory map, then it's more than clear that a flash download fails.
You have specified as RO section some part of the internal SRAM (0x20000000) and as RAM and area in external SDRAM (0x29C00C000).
I assume this works fine when you execute your  without debugger. This means that the M0 code is part of the M4 binary image and after reset the M4 relocates the M0 code into 0x20000000.
So you don't need to do any flash download.

[u]A debugger setup works like this:[/u]

1. You compile and link an application code for execution from flash
2. You the resulting binary with whatever tool to this flash memory
3. When you start the debugger, µVision just loads the map, symbols etc into the debugger program, it doesn't download anything to the microcontroller.

To make this a little bit more handy, the debugger offers to compile & link and download to flash before before the debugger connection is started, in order to ensure that the image in the microcontroller and the image in the debugger are really the same.

I attached a short training document from Keil which might be useful for you


Hope this helps,
NXP Support Team.

0 件の賞賛
返信

1,195件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by ali_asadzadeh on Sun Mar 15 22:21:49 MST 2015
Thanks, I'm aware of that, and actually I have written a dual core working project,It works perfectly. The problem is that I can not debug M0 core! A simple dual core blinky project in Keil that can be debugged with J-link would be highly appreciated.
0 件の賞賛
返信

1,195件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by TheFallGuy on Sun Mar 15 06:59:55 MST 2015
Are you aware that the m0 is held in reset until it is released by the m4? That is you have to have code in the m4 to enable the m0, and until you do that, you cannot connect a debugger to it.
0 件の賞賛
返信

1,195件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by ali_asadzadeh on Sat Mar 14 07:17:59 MST 2015
Hi,
Thanks for the info, I have checked them ,But not any lock! Would you please post a simple test project based on j-link and keil that you could debug the M0 core? Notice that I'm able to debug the M4 core, But I can not debug M0 core.
0 件の賞賛
返信

1,195件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by embd02161991 on Wed Mar 11 14:03:37 MST 2015
Hi,

Have you checked the LPCOpen software package for Dual core examples in LPC43x0 MCUs ? It can be your starting point.
http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc43xx-packages

More information on Dual core settings here :
http://www.lpcware.com/content/project/lpc43xx-dual-core-examples
http://www.lpcware.com/content/project/lpc43xx-dual-core-notes

Thanks,
NXP Technical Support
0 件の賞賛
返信