Hi Matias Holsve
That device has two peripheral AIPS buses, with some peripherals on one bus, and others in the other bus. The FTM2 peripheral is available on both buses and, as you said, if you look at the addresses for the FTM2 register, it shows two sets of register, so, there are two clock gates for the FTM2 and you need to enable the clock gate associated with the set register that will be used. That's why there are two clock gates for the FTM2.
SDK clock driver for FTM has a bug and when you enable the gate for FTM2, it enable the associated FTM2 gate in SIM_SCGC3 register, when you actually need the associated FTM2 gate in the SIM_SCG6 register. The workaround for this issue is add the line SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK;
We already award of this problem and we are working to resolve it.
Hope this information helps you and please tell us any question related.
Have a great day
Jorge Alcala
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