What happens when an interrupt occurs? (KV10 - Thumb Processor)

[mlnj]

More specifically where do I go to learn about what the processor does when it recognizes an enabled interrupt?

I'm using a FRDM-KV10Z so my first choice reference is the KV10 Sub-Family Reference Manual.  But there's not much in there that I see about interrupts.  It refers one to the ARM Cortex-M0+ Technical Reference Manual for a "full description" of the NVIC.  But the full description turns out to be a few mostly blank pages with a reference to the ARMv6-M Architecture
Reference Manual.  The problem here is that this document seems to be describing ARM architecture rather than Thumb architecture.

My understanding is that the KV10 is Thumb only.  Assuming this to be true I'd like to know how this Thumb processor reacts when it acknowledges an interrupt. What gets saved where?  Are further interrupts disabled and if they are, how can I re-enable within the interrupt handler?  What does the processor do when it returns from an interrupt?  Why don't I have to somehow acknowledge an interrupt?

Also please consider this disassembly of the entry point of some 'C' code I have written to process a UART interrupt:

          UART0_IRQHandler:
00000648:   push {r3, r4, r7, lr}
0000064a:   add r7, sp, #0
 165          s1 = *UART0_S1&0xaf;
0000064c:   ldr r3, [pc, #96]       ; (0x6b0 <UART0_IRQHandler+104>)
0000064e:   ldr r3, [r3, #0]
00000650:   ldrb r3, [r3, #0]
00000652:   movs r2, #80    ; 0x50
00000654:   bics r3, r2
00000656:   uxtb r4, r3

What I see here is that four registers are being saved, but r2 is not one of them; and r2 is being modified.  What is going on here?

Thanks in advance for any replies.

[xiangjun_rong]

Hi, Michael,

This is another documentation which address the Cortex-M4, pls refer to chapter 7,8,9 for the interrupt mechanism.

BR

Xiangjun Rong

[egoodii]

Look for:

DUI0662B_cortex_m0p_r0p1_dgug.pdf

Section 2.3.6 has this automatic-stacking info:

The 'interrupts which are disabled' by the start-of-service of one interrupt are 'those at this or lower priority', enforced by the NVIC.  Higher priority are still 'fully able' to interrupt an ISR unless the global-interrupt-enable is cleared [__disable_interrupts()].  Note that such manual over-ride of the automatic interrupt-hardware is NOT recommended in ISRs.

Interrupt generating devices generally have specific 'acknowledge' processes to follow, but the NVIC and following ARM hardware are 'self acknowledging'.  Indeed, there isn't even a special 'interrupt return', so interrupt handles don't need 'special keywords', as a 'special code' is loaded into the Link Register (LR) to indicate the exception-processing, and recognized by hardware as part of the 'normal' return operation.