Using FRDM-KL26Z board. Code developed using Kinetis Design Studio. Program is to receive a packet of data and respond with a packet of data. It ignores the first 7 packets and starts to respond to the 8th packet. Before the packet can be completely sent a reset occurs. I have separated the K20 reset out to insure it was not causing it. I have also looked at 0x4007F000 when the reset occurs but it is all zeros. I would greatly appreciate some additional thoughts on how to debug this.
已解决! 转到解答。
Hi FRANK PUTNAM,
When you do the flash operation, please disable the global interrupt, otherwise.
If the interrupt happens during the flash operation, it may cause the undesirable reset.
Wish it helps you!
If you still have question, please contact with me!
Have a great day,
Jingjing
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Hi FRANK PUTNAM,
When you do the flash operation, please disable the global interrupt, otherwise.
If the interrupt happens during the flash operation, it may cause the undesirable reset.
Wish it helps you!
If you still have question, please contact with me!
Have a great day,
Jingjing
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Is the watchdog disabled? You say you read from that address (reset status), but are you using the memory view, or actually reading the register? You might look to make sure it's indicating that a power-on reset occurred if it's really reading all zeroes.