TWR manual vs. k60 Reference manual

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TWR manual vs. k60 Reference manual

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lukas
Contributor III

I am confused

 

in TWR-K60N512  Users manual on page 16, there are side B pins B44 - B48 description as SPI_0 and usage as PTD14,13,11,15,12

but in K60 reference manual on page 239 are those pins on port D used for SPI_2.

 

Second case is about MK60N512VMD100.h

Why is the mask for SPI_0 in  /* SCGC6 Bit Fields */

defined as

SIM_SCGC6_DSPI0_MASK

and masks for other SPIs are normal

SIM_SCGC6_SPI1_MASK

SIM_SCGC3_SPI2_MASK

 

what the D before SPI0 means ?

 

Thanks

 

Lukas

 

 

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anthony_huereca
NXP Employee
NXP Employee

1) It uses SPI2 on the K60. But it's connected to the pins defined as "SPI0" as seen by the elevator. The K60 SPI0 pins are being used for something else (with all the muxing Kinetis uses) on the board, so the K60 SPI2 module was designated instead to go out to the elevator SPI pins. 

 

This means any other tower module you have that is connected to SPI0 on the elevator ( B44 - B48) will be connected to the K60 SPI2 module. I understand how that's confusing, but I hope that cleared it up.

 

2) It should be SPI0 without the D. It's due to a register name typo on the SPI0 clock gating bit, as originally it was going to be called DSPI, and then later the name was changed to just SPI. It will be fixed in the next rev of the manual (which is what the header files are generated against) and then the header files will be updated accordingly.

 

-amh

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lukas
Contributor III

I find the DSPI description in reference manual on page 1395 it was stupid question

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pende
Contributor III
#define SIM_SCGC6_DSPI0_MASK                     0x1000u#define SIM_SCGC6_DSPI0_SHIFT                    12#define SIM_SCGC6_SPI1_MASK                      0x2000u#define SIM_SCGC6_SPI1_SHIFT                     13

#define SIM_SCGC3_SPI2_MASK                      0x1000u
#define SIM_SCGC3_SPI2_SHIFT                     12

 

not that stupid....

 

what is the difference between DSPI0 and SPI1 ? Refering to manual, every SPI module (3 in this device) is a DSPI...

 

 

49.1.3 DSPI Configurations
The DSPI module always operates in SPI configuration.


 

why is then only SPI0 defined as DSPI ?

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lukas
Contributor III

and the

base pointer and registers of SPI0  are without D  :smileyvery-happy:

 

SPI0_BASE_PTR

 

 

 

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anthony_huereca
NXP Employee
NXP Employee

1) It uses SPI2 on the K60. But it's connected to the pins defined as "SPI0" as seen by the elevator. The K60 SPI0 pins are being used for something else (with all the muxing Kinetis uses) on the board, so the K60 SPI2 module was designated instead to go out to the elevator SPI pins. 

 

This means any other tower module you have that is connected to SPI0 on the elevator ( B44 - B48) will be connected to the K60 SPI2 module. I understand how that's confusing, but I hope that cleared it up.

 

2) It should be SPI0 without the D. It's due to a register name typo on the SPI0 clock gating bit, as originally it was going to be called DSPI, and then later the name was changed to just SPI. It will be fixed in the next rev of the manual (which is what the header files are generated against) and then the header files will be updated accordingly.

 

-amh

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