Hi Jonathan,
thank you for your help.
I have looked at the demo that you dent me. But i could not find the starting point when the camera start to take a pciture.
I will continue looking at the demo. Maybe i will find some hint or something like that.
In my project i am using the following components:
- A I2C component to communicate with the camera. I tried it and that works very fine.
- A PWM component to generate a PWM signal with 30 MHz (before it was 10.5 MHz) and a duty cilce of 50% (according to the datasheet i need a PWM with at least 6 MHz, so with 30 MHz i should be safe).
- A GPIO component for the hardware reset. There is a pull up resistor.
- A other GPIO component for the VSYNC signal. For the microcontroller its a input signal with no pull up or pull down resistor
In the main.c function i wrote this code:
WAIT1_Waitms(4);
PTC_Init(); //hardware reset init function. The initial value is 0. So the camera will get a reset signal (all registers are set to //default)
WAIT1_Waitms(3);
PWM1_Init(NULL); //PWM init function. The camera will get the XCLK signal (its a pwm signal with 30 MHz and 50% duty cicle)
WAIT1_Waitms(4);
GPIO_PDD_SetPortDataOutput(PTC_DEVICE,(1<<14)); //Now the hardware reset value is 1. The camera will no get a reset signal //anymore
WAIT1_Waitms(4);
PTA_Init(); //Port A init function to get the VSYNC signal from the camera
The I2C compnent i did not use because first of all i will only get the control signals (i.e. VSYNC). So i can use the default values in the register of the camera.
Then i looked the XCLK and the VSYNC signals with a logic analyzer:

Channel 0 is the XCLK signal. Channel 1 is the VSYNC signal.
As you can see the XCLK signal is a rectangle signal. But the VSYNC signal is always zero.
That means the camera did not generate a VSYNC signal.
According to the Datasheet of OV2640, the XCLK signal have to be at least 6 MHz. 24 MHz are recommended.
According the default values in the register of OV2640 the clock divider is 1. So the clock divider can not be the problem.
And i read that with the default values the frequency of PLCK will be the same as the frequency of XLCK. And with clock divider 1 it has to be 30 MHz.
I would send you my project but there is no attachment button or something like that.
But maybe you can give me a mail address and i will send you my project as a mail.
Best Regards
Armend