Hi
Here are some snippets from an SPI Flash driver in the uTasker project:
// Power up SPI2 and configure for master mode use (50MHz bus, 25MHz speed and 140ns min de-select time)//POWER_UP(3, SIM_SCGC3_SPI2);_CONFIG_PERIPHERAL(D, 11, (PD_11_SPI2_PCS0 | PORT_SRE_FAST | PORT_DSE_HIGH));_CONFIG_PERIPHERAL(D, 12, (PD_12_SPI2_SCK | PORT_SRE_FAST | PORT_DSE_HIGH));_CONFIG_PERIPHERAL(D, 13, (PD_13_SPI2_SOUT | PORT_SRE_FAST | PORT_DSE_HIGH));_CONFIG_PERIPHERAL(D, 14, PD_14_SPI2_SIN);SPI2_CTAR0 = (SPI_CTAR_DBR | SPI_CTAR_FMSZ_8 | SPI_CTAR_PDT_7 | SPI_CTAR_BR_2 | SPI_CTAR_CPHA | SPI_CTAR_CPOL);// Flush SPI FIFO and flags (required before starting transfers)//SPI2_MCR |= SPI_MCR_CLR_RXF;SPI2_SR = (SPI_SR_EOQF | SPI_SR_TFUF | SPI_SR_TFFF | SPI_SR_RFOF | SPI_SR_RFDF);// Write a single byte in a sequence (set byte with value and ulChipSelectLine with CS flag to be used)//SPI2_PUSHR = (byte | SPI_PUSHR_CONT | ulChipSelectLine | SPI_PUSHR_CTAS_CTAR0); // write a single byte to the output FIFO - assert CS line// Write the final byte in a sequence (set byte with value and ulChipSelectLine with CS flag to be used)//SPI2_PUSHR = (byte | SPI_PUSHR_EOQ | ulChipSelectLine | SPI_PUSHR_CTAS_CTAR0); // write final byte to output FIFO - this will negate the CS line when complete// Wait for reception to complete//while (!(SPI2_SR & SPI_SR_RFDF)) {}// Read single data byte from FIFO input//x = (unsigned char)SPI2_POPR;
// Clear flag - the flag is not self-clearing and needs to be reset by code//SPI2_SR |= SPI_SR_RFDF;
This may or may not help (?). The project includes drivers for ATMEL, ST and SST SPI Flash devices - the SPI and the attached devices are simulated for simple verification and project developing/testing.
The drivers use the FIFO queuing and the automatic Chip-Select control. The main thing to be aware of is that the reception flag is not self clearing and so one has to be a little careful that it is not left set from previous use, leading to reads that are made too early.
Regards
Mark
