MK02FN64VFM10 PIT (and interrupts >63) not working

[degry]

I have a MK02FN128VLH10: I have trouble to get the PIT1 generating interrupts. (KDS3.0 with KSDK1.2.)

Also PIT0,2,3 are not working.

PIT clock is enabled. Global interrupts are enabled.

PIT is running and interrupt flag TIF set in TFLG1.

Systemcontol - ICSR - VECTACTIVE = 0x41 (indicating vector 65 = PIT1).

Registers Primask = 0; So interrupts are not blocked.

At the correct vector table position: I see the address of the handler. If I dissassemble at this address, I see the correct handler code.

But the processor is not jumping to the handler!

Then I tried to invoke a software interrupt:

  enable_irq (PIT1_IRQn);

  EnableInterrupts;

  NVIC->STIR = PIT1_IRQn;

It is not jumping to the handler PIT1_IRQHandler().

However, with the above code, if I take any interrupt number < 63, the software interrupt works!

  enable_irq (UART0_RX_TX_IRQn);

  EnableInterrupts;

  NVIC->STIR = UART0_RX_TX_IRQn;

Then it jumps to UART0_RX_TX_IRQHandler().

Or even:

  enable_irq (Reserved53_IRQ);

  EnableInterrupts;

  NVIC->STIR = Reserved53_IRQ;

Then it jumps to Reserved53_IRQHandler().

Bad luck: the PIT starts at 64...

Test:

  enable_irq (Reserved71_IRQ);

  EnableInterrupts;

  NVIC->STIR = Reserved71_IRQ;

It does NOT jump to Reserved71_IRQHandler().

I get a default interrupt or nothing happens.

Any idea?

patrick

[mjbcswitzerland]

Hi Patrick

Where are your vectors located (i.e. what value does VTOR have)?

If it is not divisible by 0x200 there can be stange effects that some vectors work as expected but some are shifted.

Regards

Mark

Kinetis: µTasker Kinetis support

K60: µTasker Kinetis TWR-K60N512 support  / µTasker Kinetis TWR-K60N512 support  / µTasker Kinetis TWR-K60F120M support

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[degry]

Hello Mark,

They are at 0x00002100...

BR

Patrick

[mjbcswitzerland · Accepted solution]

Patrick

0x00002100 is not a valid address for a Cortex-M4 device with more than 64 interrupts (or 47 peripheral interrupts).

See the following for an explanation: Vector Table Offset - is this exected behaviour??

0x00002000 or 0x00002200 are OK for the K02.

Regards

Mark

Kinetis: µTasker Kinetis support

K60: µTasker Kinetis TWR-K60N512 support  / µTasker Kinetis TWR-K60N512 support  / µTasker Kinetis TWR-K60F120M support

For the complete "out-of-the-box" Kinetis experience and faster time to market

[degry]

Hello Mark,

Moving the table to 0x00002200 did the job! Thanks for the providing the solution!!

Do you also know?:

If I erase program flash (for updating my application), it it then recommended to implement the FlashCommandSequence in RAM?

I did that for K10.

If erasing when executing from program flash, most of the times it is OK but nevertheless, I moved this sequence to RAM since it was recommended.

Is this the same for K02 and K22?

BR

Patrick

[mjbcswitzerland]

Patrick

Unless you have code that is operating in one Flash plane and performing Flash operations in "another" Flash plane it is necessary to operate the code from RAM. If interrupts could run in the same Flash plane as the one that operations are being performed on, interrupts should also be disabled.

If this rule is generally respected, whatever the code/flash plane arrangements in the SW and the HW used, it will then operate on all parts without any specific considerations being needed.

Regards

Mark

Kinetis: µTasker Kinetis support

K22: µTasker Kinetis FRDM-K22F support  / µTasker Kinetis TWR-K22F120M support

K60: µTasker Kinetis TWR-K60N512 support  / µTasker Kinetis TWR-K60N512 support  / µTasker Kinetis TWR-K60F120M support

For the complete "out-of-the-box" Kinetis experience and faster time to market