LLS state and LLWU module

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

LLS state and LLWU module

1,007 Views
renka
Contributor II

Hi,

 

I'm working with K60 on Tower board.I have a question about LLWU module and enter-exit from LLS mode. 

My simple project  example code has

  • Start system like in Freescale example projects
  • Start the lpt timer and lpt interrupt.
  • In loop:
    • Some artificial delay function
    • Enter to LLS mode 

The LLWU ISR function is also defined in vector isr table. From datasheet the LLWU isr must not be masked.

The result is

  • The program enters to LLS mode
  • LLWU wakeup isr is occurred
  • LPT isr is occurred right after LLWU Isr
  • But after LPT Isr,the LLWU Isr is occurred again,so LLWU Isr is encapsulate LPT Isr.(I right a simple log to see this scenario).Could you help me to understand, why LLWU Isr is “pending” again after LPT Isr?

 

The second question is what need to be in the body of LLWU Isr function? Now I didn’t do nothing in the context of LLWU Isr,and after LPT ISR I make the following:

“  NVICICPR0|=(1<<21); //Clear LLWU interrupt

   NVICISER0|=(1<<21); //Enable LLWU interrupt

The additional LLWU Isr didn’t occurred, but the J-link disconnected from CPU.

Any help will be welcomed!!!Thanks.

 

0 Kudos
2 Replies

409 Views
philip_drake
NXP Employee
NXP Employee

Hi,

It is very likely that the LPTMR isr you have created does not clear the LPTMR flag.  A good way to check this is in run mode.  Once the flag crearing is working then you can re-enable the LLS mode entry.

For a complete guide to the low power modes please see an application note I've written on this subject.  AN4503.

There are a number of other things to consider.  One is the clearing of the LPTMR flag sequence and code execution timing.

The clearing of the LPTMR flag takes a number of cycles (up to 7 bus cycles).  If you clear the LPTRM flag with a write to an LPTRM register then you should do a read of the LPTMR register to make sure the flag is cleared before exiting the isr.

This is what I put in my LLWU isr.

  if (LLWU_F3 & LLWU_F3_MWUF0_MASK) {

       printf("****WUF3_MWUF0 IF  LPTMR  *****\r\n");

         SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;

         LPTMR0_CSR = ( LPTMR_CSR_TEN_MASK | LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK  );

         LPTMR0_CSR |=  LPTMR_CSR_TCF_MASK;   // write 1 to TCF to clear the LPT timer compare flag

   }

If you do this the LPTMR isr will not be taken and both the LPTRM flag and the LLWU flag are cleared.  Writing only to the LLWU module llag is not required and will not clear the LPTRM flag.

I hope this helps,

Philip

0 Kudos

409 Views
namfuak
Contributor III
You will receive LLWU interrupt constantly if LLWU wakeup flags are not cleared. For LPT you need to clear LLWU_M0IF bit (at least in K60). It can be done in LLWU ISR, or in LPT ISR. Clearing LLWU wakeup flags is the only thing I do in LLWU ISR.
0 Kudos