Kinetis UART SFIFO reserved bit becomes set during Rx underflow (using PE)

[luc28]

I am using the Processor Expert serial LLD component to send and receive data with UART1 on the Kinetis K10DX128VLL7.

At some point in time, the UART keeps the last character in the buffer and releases it when the next byte comes in .

To recreate the problem, I use the debugger to stop the processor, send a message longer than the uart buffer(>8), and start the processor.

This creates an overflow in the uart and the uart keeps the last character in the buffer (until the next one comes in, then the previous one is released and the new one is kept).

This also causes reserved bit in the SFIFO register to be set.

Using AS1_Init and AS1_Deinit functions, I have tried to reset the UART but that simply prevents me from receiving any data at all and the reserved bit is still there.

Questions:

What does that bit mean? (SFIFO = 85 where 0x4 bit mask is reserved)

How can I prevent that reserved bit from being set?

How can I reset the UART in this condition?

KinetisUart1RegistersAfterUnderflow

KinetisUart1RegistersAfterSystemResetAndInitialisation

Thank you

Luc

[luc28 · Accepted solution]

The problem seemed to have disapeared as we fixed the collisions on the half duplex serial link

[gerry26]

Hi Luc,

I have a similar problem to the one you described above and I would like to ask you to elaborate on the nature of your solution.

In my case there is an UART overflow, caused by interrupt long latency, which leaves the system with no active interrupt but with a char in the buffer.

This prevents from new char to be received. the only thing that releases the UART interface is D read.

Following this read the interface is released and the RX flow runs once again.

Tnx,

Gerry