Kinetis K64 Open Drain Configuration

[kevinstevens]

I need to connect my K64 to a Telit DE910 module (via a NimbeLink or Janus baseboard) and it has a 1.8V max on some of the IO lines. I am taking care of the level conversion for the TTL signals with external components, but was hoping to reduce part count and utilize the processor's open drain configuration for some of the IO lines.

The specifications call for an open collector driver and that the module has an internal pullup resistor.

My question is what exactly the configuration is within the K64 when configured as Open Drain. The data sheet indicates that it must be pulled up externally to VCC (3.3V in my case) and the reference manual doesn't really explain in detail the configuration. However, through testing I have found that the output seems to be internally pulled up (seemingly a weak pullup) to VCC. Can anyone confirm this? Do we know what resistor value is being used or if the internal pullup can be disabled completely? Ideally I want a classic open drain driver without the pullup so I don't have to worry about exceeding the module's Vmax.

I have connected an external pullup to a 1.5V battery just for testing and found that with a 10K resistor the signal line reads over the battery voltage by ~0.15V and with a 1K it is about 0.5V over the battery voltage. This was done on a freedom board.

Using processor expert there doesn't seem to be a way to disable the internal pullup. Any help or insight would be much appreciated.

[kevinstevens · Accepted solution]

I received the following reply from one of my contacts after not having any luck here.

The open drain feature in the Kinetis K series in mainly intended for bidirectional signals, like I2C. And it expected that the signal is pulled up to the MCU VDD voltage.  With the pad structure, there is a leakage path to VDD like you found.

As Xiangjun suggested, you can power the K64 at 1.8V if you want it all on one supply.  Or if that is not an option for you, then using voltage translators between 3.3V and 1.8V should work.

[kevinstevens]

Hey guys thanks for the responses. However, this doesn't seem to work. We added this into the code and are still seeing 0.15V over the battery voltage on the pin when it is configured as an open drain output and pulled up using a 10K resistor. For some reason this doesn't seem to be clearing the pullup. Any other thoughts?

Additionally, we found that when the pin is disabled the voltage reads correctly. However, as soon as we enable it as an open drain GPIO the voltage increases. Our understanding is that the open drain should act in the same manner as the pin being disabled. Is this incorrect with how the K64 implements open drain?

Kevin

[xiangjun_rong]

Hi, Kevin,

As Mark said that you should disable internal pull-up resistor so that you can use external 1.8V pull-up resistor using the code as Mark told you. For each pin, there is a port register PORTX_PCRY, when the PE bit(bit 1) is cleared, the internal pull up/down is disabled, in the case, external pull-up resistor will function if you set the pin in output and open drain mode.

Regarding the input logic voltage of K64, pls refer to section 2.2.1 Voltage and current operating requirements in data sheet of K64, the minimum voltage of "logic 1" is 0.7*VDD=0.7*3.3V=2.3V, so the 1.8V is not regarded as logic 1 in 3.3V system.

I suggest you use a transceiver such as 74ls244 like chip which is powered by two power supply voltage. As you know that the K64 can be powered by voltage from 1.8V to 3.3V, if you powered the K64 with 1.8V, it is an option, but all the K64 output voltage will be 1.8V.

Hope it can help you.

BR

XiangJun Rong

[mjbcswitzerland]

Hi

PORTX_PCRY &= ~(0x00000003); disables pull up on port X, pin Y

Regards

Mark