Process Expert UART Multidrop parity setup

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Process Expert UART Multidrop parity setup

Contributor I

Dear Sir,

Processor Expert generates different registry addresses, as it was done before for UART having

#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C). I need setup it for using RS485.

PEx creates me for UART with even parity 


void AS2_Init(void)
SerFlag = 0x00; /* Reset flags */
/* UCR1: ??=0,MISC=3,TC=0,RC=0 */
setReg8(UCR1, 0x30U); /* Reset UART transmitter */
/* UCR1: ??=0,MISC=2,TC=0,RC=0 */
setReg8(UCR1, 0x20U); /* Reset UART receiver */
/* UMR11: RXRTS=0,RXIRQ=0,ERR=0,PM=0,PT=0,BC=3 */
setReg8(UMR11, 0x03U); /* Set the UMR1 register */
/* UMR21: CM=0,TXRTS=0,TXCTS=0,SB=7 */
setReg8(UMR21, 0x07U); /* Set the UMR2 register */
/* UCSR1: RCS=0x0D,TCS=0x0D */
setReg8(UCSR1, 0xDDU);
/* UBG11: Divider_MSB=0 */
setReg8(UBG11, 0x00U);
/* UBG21: Divider_LSB=0xF0 */
setReg8(UBG21, 0xF0U);
HWEnDi(); /* Enable/disable device according to status flags */

How to modify UART_UMR_PM registry to make multidrop parity?




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3 Replies

NXP TechSupport
NXP TechSupport


Which ColdFire product you are using? Please provide the part number.

best regards,


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Contributor I

Hi Mike,

I am using MCF5213ACF80.



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NXP TechSupport
NXP TechSupport


First of all, sorry for the later reply.

I could find below support record info about ColdFire(MCF5282) UART multidrop mode.  Hope below info could be helpful:
MCF5282 is using the same UART module with MCF5213.

As part of my recent development effort I’m trying to configure one of the UARTs of MCF5282 in multi-drop mode. The ISR is working fine in address detection mode but only once; then onward I’m not getting the interrupts. These are the set of operations that I’m performing on the UART2 module. Initialization() { Reset RX and TX; // Reset Mode register so it points to UMR1 Aux->AuxRegs->CommandReg->Register =AUX_RESET_MODE_PTR; Aux->AuxRegs->Mode1Reg->Register = (BYTE)0|(CFAUX_PARITY_MULTIDROP_ADDR|Aux->Line.DataBits); // Disable the receiver so that it wake up when we get the next address character Aux->AuxRegs->CommandReg->Register =AUX_RX_DISABLE; Do rest of the UART initialization; } UART2ISR() { if (RxReady) { while ((RxReady)||(FIFOFull)) { Do the necessary processing; // Must read the Rx byte to clear the interrupt. // This also advances/clears the statReg bits to the values for the next queued byte. RxByte = Aux->AuxRegs->RxBufReg->RxByte; // Check if it is my own address or broadcast address if ((MY_ADDRESS == RxByte) || (BCAST_ADDRESS == RxByte)) { // Data recording mode // Reset mode register pointer before access... Aux->AuxRegs->CommandReg->Register =AUX_RESET_MODE_PTR; Aux->AuxRegs->Mode1Reg->Register = (BYTE) 0 | (CFAUX_PARITY_MULTIDROP_DATA| Aux->Line.DataBits); Aux->AuxRegs->CommandReg->Register = AUX_RX_ENABLE; } else if (MESSAGE_TERMINATOR){ // Address detection Mode ParityReg = CFAUX_PARITY_MULTIDROP_ADDR; // Reset mode register pointer before access... Aux->AuxRegs->CommandReg->Register =AUX_RESET_MODE_PTR; Aux->AuxRegs->Mode1Reg->Register = (BYTE) 0 | (CFAUX_PARITY_MULTIDROP_ADDR | Aux->Line.DataBits); Aux->AuxRegs->CommandReg->Register =AUX_RX_DISABLE; } Address: Bit9 = Set; Bit8 to Bit1 = address Data: Bit9 = Clear; Bit8 to Bit1 = Data Terminator: Bit9 = Set; Bit8 to Bit1 = 0xFF Can you please help me with this.
Regarding your inquiry, I am not sure if you have configured UART2 to work in interrupt mode, to do this in user_config.h you need to enable ITTYC = 1. The MCF5282 only supports 5–8 data bits plus parity. The parity bit could be used as the 9th bit. There are the UMR1n[PM; PT] bits which it is in position to set up either for Force parity, or for Multidrop mode. In multidrop mode, the address character has the 9th bit==1 and data character has the 9th bit==0 (8bit character is assumed). Any way, this will require a change in the UMR1n mode register before a character is pushed to the transmit buffer. A change in UMR1n needs to perform RESET MODE REGISTER POINTER and RESET TRANSMITTER/RECEIVER commands (UCRn command register) in advance.

About UART UMR register setting, there with below info for your reference:

Qustion: There are two registers _UMR1 and _UMR2. But the have the same ipsbar-offset!!! How should this work?
Answer: There is one pointer to UMR1n and UMR2n registers.
The UMR1n can be read or written when the mode register pointer points to it
> After Reset of CPU
After UMR1n is read or written , pointer points to UMR2n and can UMR2n can be accessed .
UMR2n access doesn't update the pointer !

I attached related code for your reference.

Wish it helps.


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