Hello,
The ISR code to set the next output compare value need not be very complex - my estimate is a total of 43 cycles to complete. This assumes that the default TMOD value is not changed. Assuming use of a 6.4MHz bus frequency, this would then require 6.7 microseconds for the ISR processing. A 6.4MHz bus frequency would also give a timer overflow period of nominally 10.24 milliseconds, very close to what you need.
The minimum allowable audio frequency would be 50 Hz, and the maximum I suspect would need to be kept below about 2000 Hz (with an interrupt occurring every 250 us, or 1600 cycles).
I am not familiar with LIN to know what are the critical timing issues related to the handling of a message. However, I might suspect there would be more possibility of the LIN message processing, within an associated ISR, causing disruption to the tone output.
For the estimate given above, the following ISR code was assumed for TIM channel 0. The estimate also included 9 cycles required tor entry to the ISR.
BCLR CH0F,TSC0 ; CLEAR FLAG
LDX TCH0H
LDA TCH0L
ADD PERIODVAL ; LS BYTE OF TONE HALF PERIOD
PSHA
TXA
ADC PERIODVAL+1 ; MS BYTE OF TONE HALF PERIOD
STA TCH0H
PULA
STA TCH0L
RTI
Regards,
Mac