PE generated Timer interrupt is running slow

[Geoff_L]

I used PE to create a period timer on an MC9S08AC48, for some reason the timing of the pulses is off by a factor of 2-3   please see the attachment for a screen shot of how I configured the timer.  

I'm trying to use the timer TPM3 to help control communications  with a one-wire device.   There are four specific timed pulses that I need to bit bang - a 15uS pulse, a 67uS pulse, a 240uS pulse and a 480uS pulse.    I configured the bean to provide these options.  I have also attached an image of the setting for the four times, and the output of my bit-banging.

The way I've approached the bit banging is to write a zero to the one wire bus, then set the timer to interrupt after a certain amount of time and which then writes a one to end it. 

If you look at the attached bit bang, you can see that when I create a low going pulse, and then enable and set the timer for 67uS, as in the code below, the pulse I get is 160uS, not 67uS.   Can anyone offer some advice on how to remedy this problem?

void OW_WriteBit(bool sendbit){

                OW_TXBIT(0);  //every write is preceded with a 1-0-1 transition

                if(sendbit) OW_TXBIT(1);

                (void)ONEWIRE_TMR_SetPeriodMode(ONEWIRE_TMR_PM_67_0us);

                (void)ONEWIRE_TMR_Enable();

}

void OW_TIMER_Int(void)

{

                (void) ONEWIRE_TMR_Disable();  //shut down the counter so it doesn't keep going and cause another interrupt

               OW_TXBIT(1);  //release the bus - let the device respond

}

[Geoff_L]

Some more information I have found as I worked on this.

It turns out that the timer is not running slow, but it seems to have a delay before it's first interrupt.  When I stop re-initializeing the timer every time, then the time is correct. 

Why does initializing the timer cause a delay in when the interrupt occurs?    I need to create a varialble delay time - what is the appropriate way to get 15uS, 67uS, 240uS or 480uS delays?

Thanks

Geoff

[ProcessorExpert]

Hello,

In generall, I think that the problem with difference between the first period  and regular periods is caused by handling ISR.

Since you have not provided information about CPU component settings I guess you are using low value of „Internal bus clock“ frequency in comparasion with period that you need to achieve and that leads to problem as is described above.

ISR handling can be minimized by increasing internal bus clock frequency (e.g. 20 MHz). In this case I  measured difference 600ns between first and regular periods in case of 15us period.

For more details please find enclosed example project.

best regards
Vojtech Filip
Processor Expert Support Team