Mass Erase of MC9S08QE8 - never get completion

[lazde]

I have been using the 908QB8 and now moving to the 9S08QE8.  When attempting to mass erase or page erase or byte program flash on the 9S08QE8 from a RAM resident routine, I am not able to read FCDIV to verify it have been written.  I am able to check and clear errors in FSTAT.  I load HX with the flash address and A with data, then write it (all in a RAM based routine) then I follow the procedure to load FCMD and then set FCBEF.  After the 4 cycle wait, FSTAT returns as 0 so FCCF never sets to indicate completion.  Maybe there is something I should be doing prior to all of this possibly in the protection area but nothing seems to work.  All errors are cleared prior to executing this code.

Any ideas?  Is there something special with the QE8?

[lazde]

So far I have found the KEYACC bit in the FCNFG register must be set.  If this bit is set at startup, code running in RAM can access the FLASH registers in high page memory.

[lazde · Accepted solution]

The Reference Manual for the QE8 does not explain Bit 6,the FLS bit, in the System Clock gating Control 2 register (SCGC2).  It covers all the other bits but not the FLS bit.  If the FLS bit is set to 0, this will disable reading the FLASH high registers in $1820-$182B.  Once enabled, FLASH can be erased and reprogrammed in-application.

[Stryphe]

OMG thank you so much!

I am working on the MC9S08LL36 and the user manual ALSO neglects the FLS bit explanation in SCGC2. It seems it is a typo that is carried through all the RM's I have for the various Freescale micro's I have used.

The FLS bit was set to zero in SCGC2 and as a result, I could NOT write to FCDIV no matter what I did.

I would write to it, and directly afterwards find reads to return 0x00. As usual, Freescale had NO comment on it in their reference manual or application notes. There are MANY situations like this where there is one determining factor and they just neglect to mention it, wasting days of time. To note was the LCD and its requirement of the TOD for using the aux clock if you are using an external crystal.

Many thanks for this thread and your solution even though it wasn't related to my micro, it still helped me solve my FCDIV issue

[J2MEJediMaster]

Let us see about getting this hole in the documentation plugged. Please file a Service Request on this. Click here to go to the service request page and for the Category choose Hardware Product Support. Be sure to describe in the detail the error and the page number of the of the documentation in question.

---Tom

[Stryphe]

Hi

I indicated in my current open service request with support@freescale.com that it was in multiple reference manuals (QE8, LL64 so far) under "5.8.11 System Clock Gating Control 2 Register (SCGC2)" and "Table 5-15. SCGC2 Register Field  Descriptions" in my LL64 RM, Pg100, missing field 6 (FLS).

However, my LL16RM has it correctly incidently, so I may have been a bit hasty to jump on the band-wagon

Thanks