I'm looking at some code in an old and working (for over a decade) product.
It is an MC68HC908GZ60. It has a low-power idle loop that calls STOP to save power.
It has an external 4MHz Crystal and uses the PLL to generate 32MHz and an 8MHz bus clock. The MCU is running from that clock (the PLL and not the XTAL).
OSCENINSTOP and SSREC are set so the oscillator keeps running and the recovery is fast. But (according to the manual), the PLL stops in this Stop Mode.
The code wakes up every 2ms from a Timebase Interrupt.
I think that means that the CPU wakes up with the PLL disabled, and so has to wait until it comes up. It only waits 32 clocks and not 4096 because SSREC is set.
The code consists of 10 "stop" instructions in a row followed by a "check to see if should wake up" sequence. The following oscilloscope shows 4 short wakeups at 2ms intervals, followed by the long one (3ms) when it runs the check. Then it goes back to the short ones. The magnification is of the "long one" startup edge.
The signal above is the CGMXFC signal on the CPU. That's the input to the PLL's VCO, and would seem to indicate that it takes 33us for the PLL to get back to running at the right frequency. I don't know what frequencies it is running at when CGMXFC is rising from zero.
Here's one of the short ones. It is only getting to about half of the working voltage (and possibly frequency) before the running code drops into the next STOP instruction and the PLL shuts off again.
I think the above means that the CPU exits the stop mode and is then running on an unstable clock from the PLL. It isn't waiting for the PLL to be synchronized (as it managed to enter stop mode and disable it before it got fully on).
It this a valid thing to do?
Or should the code switch back to running from the crystal before executing "stop" and should wait (in software) for the PLL to be synchronized ("(REG_PCTL & PBWC_LOCK)") before manually switching back to the PLL clock?
I'm reading the "MC68HC908GZ60 Rev. 6.0 04/2007" Data Sheet.
There's nothing in the manual detailing how to get into and out of STOP mode with the PLL running, and I can't find any App Notes on this either. I can find one for the later HCS08, but not HC08. There's no timing information specific to this condition.
One old unit is resetting with "SRSR[ILOP]" (Illegal Opcode) every couple of hours, and I'm wondering if this is related.
The FLASH is detailed to enter a "Standby Mode", but there's nothing detailing how long it takes to exit that mode (in "21.15 Memory Characteristics"). There's a "Low Power Modes" Chapter, but it doesn't even mention the Memory/Flash system.
As far as I can tell, the PLL takes 5-25ms to lock (21.9.3 CGM Acquisition/Lock Time Information), so running in 32 clocks seems a little fast.
Tom
Here's some more information.
I've programmed the chip to emit The Bus Clock divided by 4 onto MCLK so I can see what that clock is doing. This is the same clock (or derived from the same clock) that the CPU is running from. It is programmed to run from the PLL with the resulting Bus Clock being 8MHz.
The BLUE trace is the CGMXFC pin. That's the pin with the filter on it that provides the voltage that runs the VCO. The Yellow signal is MCLK, which is BUSCLK/4 and so is normally 2MHz. The Blue signal can be seen taking about 30us to stabilize, at which point MCLK is now stable at 2MHz. The Blue trace starts rising when the previous STOP instruction is exited.
The following is exit from STOP followed by quick entry into STOP again. The clock starts out at about 550kHz and gets to 1.3MHz before the next STOP instruction.
If I set the oscilloscope to trigger on positive cycles less than 250us, I get it capturing 230us cycles, which corresponds to a bus clock of 8.7MHz. That means the PLL is overshooting the target frequency, and makes the CPU run faster than its specified maximum of 8MHz.
So running from the PLL when the PLL is stopped (and then starting) looks like a very bad idea.
There's just no mention of this in the Reference Manual or any of the App Notes that I can find.
There's an interesting extra paragraph in the MC68HC908GZ8 manual that isn't in the corresponding sections of the MC68HC908GZ16 or MC68HC908GZ60 manuals. In the "Low Power Modes" chapter, the "Clock Generator Module (CGM) - Stop Mode" section has the extra part shown in RED:
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP
instruction disables the CGM (oscillator and phase-locked loop) and holds low all
CGM outputs (CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two
driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control
register (PCTL), thereby selecting the crystal clock, CGMXCLK, divided by two as
the source of CGMOUT. When the MCU recovers from STOP, the crystal clock
divided by two drives CGMOUT and BCS remains clear.
If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop
is shut off, but the oscillator will continue to operate in stop mode.
I wouldn't have expected the GZ8 and the other ones to be that different. That automatic switching to a stable clock looks like a very good idea, and I don't know why the GZ60 doesn't do that. Or maybe it is doing that, the manual is at fault and we've never done enough measurements to notice it is running at quarter speed.
Tom
