COP watchdog in STOP3 mode for HCS08

[kaes]

The next scenario been given:

1. watchdog enabled with 1KHz clock source

2. RTI enabled in sleep mode and raised cyclically at 8ms driven by the same clock source

3. the routine of the interrupt does not clear the watchdog counter

=> the MCU is not reset by the watchdog reset

Any clue? Thank you.

[bigmac]

Hello, and welcome to the forum.

Where have you placed the STOP instruction?  This would usually be located somewhere within the main loop.  When wakeup from Stop 3 mode occurs, the RTI ISR code will be executed.  When this is completed, execution will continue at the instruction immediately following the STOP instruction.  It is usual to clear the COP timer within the main loop, so this may prevent COP timeout from occurring.

Regards,

Mac

[kaes]

Hello and thank you for the reply,

I think that I didn't explain enough the scenario:

I have a application that runs in high-power mode and also in low-power mode (in this case, STOP3 mode). To enter in STOP3 mode, STOP instruction must be executed. In STOP3 mode, the only code that is executed is the body of the RTI that is raised cyclically at 8 ms. It has as clock source the 1KHz clock, that also is input in the COP watchdog. In the ISR of the RTI the watchdog counter is not cleared, so I would expect that after a time period the watchdog will reset the MCU. But nothing happens, as the watchdog is disabled. But all the configuration registers are in good shape.

[bigmac · Accepted solution]

Hello,

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kaes wrote:

I have a application that runs in high-power mode and also in low-power mode (in this case, STOP3 mode). To enter in STOP3 mode, STOP instruction must be executed. In STOP3 mode, the only code that is executed is the body of the RTI that is raised cyclically at 8 ms. It has as clock source the 1KHz clock, that also is input in the COP watchdog. In the ISR of the RTI the watchdog counter is not cleared, so I would expect that after a time period the watchdog will reset the MCU. But nothing happens, as the watchdog is disabled. But all the configuration registers are in good shape.

---

There does seem to be a little confusion about the operation of Stop 3 mode.

Whilst stop mode is active, no code is being executed as the bus clock is disabled.  You appear to be using the RTI counter as a wakeup source, with a timeout period of 8 milliseconds.  The wakeup process will restore the bus clock so that further code may continue to execute.  The ISR code for the RTI, will immediately execute.  When this has finished, the program counter will be located at the instruction immediately following the STOP instruction that caused Stop 3 mode to be entered.  Normal operation of the MCU will then continue until a further STOP instruction is encountered.

Whether COP timeout occurs, or not, will depend on what occurs between the execution of successive STOP instructions.

For some MCU types (e.g MC9S08AW) the COP timer is explicitly not available as a wakeup source, which means that the COP timer has to be in a disabled state whilst Stop mode is active.  It would just not make sense for the COP timer to continue to run, since there is no code execution to go haywire.

Regards,

Mac

[kaes]

Hello bigmac,

Thanks for the response, you maked all things clear now.

[rocco]

Hi Kaes,

You did not mention which S08 you were using, but the behavior you are experiencing is the correct behavior for some of the  S08 members. Here is a snippet from the DZ datasheet:

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If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either
background debug mode or stop mode and begins from zero upon exit from background debug mode or
stop mode.

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So entering stop mode in the DZ would have the same effect as clearing the watchdog.

[kaes]

Hello and thank you for the response rocco,

MC9S08AW16A is the MCU used, and I am aware about the datasheet snippet that you mentioned. But from what I understand the watchdog counter is only cleared upon STOP mode, and not disabled. So in STOP mode the watchdog is active, if it has as clock source the 1KHz clock. Still no reset triggered by the watchdog occurs. Maybe I understand the all description wrong.