How to generate microsecond delay with SysTick on KL25

Document created by Fang Li Employee on Dec 29, 2018
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The SysTick is a part of the Cortex-M0+ core and so is not chip specific - for details of the Cortex core you generally need to use ARM documents. For SysTick:


By summary, the SysTick is configured through four registers:

1. SysTick Control and Status(CSR): basic control of SysTick e.g. enable, clock source, interrupt or poll

COUNTFLAG: count-down flag, if down to 0, then this bit will be set to 1, otherwise, it will be 0.

CLKSOURCE:  when using internal core clock, it will be 1. If using external clock, it will be 0.

TICKINT: interrupt enabled when setting to 1.

ENABLE: counter enabled when setting to 1.


2. SysTick Reload Value(RVR): value to load Current Value register when 0 is reached.

3. SysTick Current Value (CVR): the current value of the count down.

4.SysTick Calibration Value(CALIB): contain the number of ticks to generate a 10ms interval and other information, depending on the implementation.

TENMS: tick value for 10 ms.


To configure the SysTick you need to load the SysTick Reload Value register with the interval required between SysTick events. The timer interrupt or COUNTFLAG bit is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks. If a period of 100 is required 99 should be written to the SysTick Reload Value register.


See attached code on how to generate microsecond delay.