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3GB LPDDR4 Stress failed on i.MX8MINI custumized board

Question asked by PRAMOD KUMAR on Nov 11, 2019
Latest reply on Nov 14, 2019 by igorpadykov
DDR Stress test failed  as script is run for 2GB LPDDR4 as available with test tool in  while our board has 3GB LPDDR4.
The log of Stress Test is given below:
############# STRESS TEST LOG START HERE #################################
 
*************************************************************************
       MX8 DDR Stress Test V2.10
       Built on Mar  5 2019 14:24:57
*************************************************************************
 
--Set up the MMU and enable I and D cache--
   - This is the Cortex-A53 core
  - Check if I cache is enabled
  - Enabling I cache since it was disabled
  - Push base address of TTB to TTBR0_EL3
  - Config TCR_EL3
  - Config MAIR_EL3
  - Enable MMU
  - Data Cache has been enabled
  - Check system memory register, only for debug
 
   - VMCR Check:
   - ttbr0_el3: 0x93d000
   - tcr_el3: 0x2051c
   - mair_el3: 0x774400
   - sctlr_el3: 0xc01815
   - id_aa64mmfr0_el1: 0x1122
 
  - MMU and cache setup complete
 
*************************************************************************
            ARM clock(CA53) rate: 2000MHz
            DDR Clock: 1500MHz
 
============================================
        DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select:   2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================
 
MX8M-mini: Cortex-A53 is found
 
*************************************************************************
 
============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1500Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1500Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS
 
============ Step 2: DDR memory accessing... ============
....[Result] OK
 
============ Step 3: DDR parameters processing... ============
[Result] Done
 
Success: DDR Calibration completed!!!
'lpddr4_timing.c' is created!
DDR Stress Test Iteration 1
DDR frequency change is unsupported at present
  --------------------------------
  --Running DDR test on region 1--
  --------------------------------
 
t0.1: data is addr test
...Address of failure: 0x00000000A0000000
Data was: 0x000000005FFFFEC0
But pattern should match address 0x0000000060000000
 
Is 3 GB DDR4 work on i.MX8MINI CPU or we replace the 3GB LPDDR4 with 2GB LPDDR4.
Regards,
Pramod Kumar

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