I have question about delay step of MMDC Read and Write calibration.
Could someone answer for the delay step ?
The following description is in the MMDCx_MPRDDLCTL of reference manual.
(RD_DL_ABS_OFFSET0 / 256) * MMDC_CH0 AXI clock (fast clock).
So for the default value of 64 we get a quarter cycle delay.
I understand that the AXI Clock (fast clock) is recognized as 1/2 of SDRAM Clock.
(264 MHz when the SDRAM Clock is 528 MHz)
AXI Clock (fast clock) is 1/2 of SDRAM Clock.
Is the above understanding correct?
Is it actually 1/256 unit of SDRAM Clock?
It's easy to understand that a quarter cycle is the default that takes the middle of data that changes in half a cycle (DDR).
However, if it is 4/1 of the AXI clock, it will be 1/2 of the DDR clock, and the default value and the adjustment range are too large.
In addition, the calibration log by the test tool is actually 1 → 0 → 1 The changing 0 (OK) range is also equivalent to an average of 76 steps in the OFFSET value, which translates into an impossible result exceeding 1124 ps and a half cycle (947 ps) of the SDRAM clock.