AnsweredAssumed Answered

iMX7S clock inputs / outputs (2nd time)

Question asked by Andrea Pastega on Dec 11, 2018
Latest reply on Dec 17, 2018 by Artur Petukhov

Hello,

please refer to question iMX7S clock inputs / outputs ,

it is automatically "ASSUMED ANSWERED" but actually it's not, I don't know how to remove the answered check.

 

I read this chapter, but my doubts still remain...

 

• CLK1P/N + CLK2

While CLK1 should be I/O, CLK2 should be input only (from another post in this forum).
Where are connected these signals? In schematics at pages 495-499 there's no sign of them.

How should I configure them?

 

• CCM_ENET1_REF_CLK / CCM_ENET2_REF_CLK / CCM_ENET3_REF_CLK

These signals appear to be output only to me. Could you confirm this?

Where are connected these signals? In schematics at pages 495-499 there's no sign of them.

I suppose they are derived from interbal signals ENET1_REF_CLK_ROOT or ENET2_REF_CLK_ROOT or ENET_PHY_REF_CLK_ROOT, but there's no explanation at all about this.

How should I configure them?

 

Thanks

Andrea

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