iMX7S clock inputs / outputs (2nd time)

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

iMX7S clock inputs / outputs (2nd time)

Jump to solution
565 Views
andpas
Contributor II

Hello,

please refer to question iMX7S clock inputs / outputs ,

it is automatically "ASSUMED ANSWERED" but actually it's not, I don't know how to remove the answered check.

I read this chapter, but my doubts still remain...

 

• CLK1P/N + CLK2

While CLK1 should be I/O, CLK2 should be input only (from another post in this forum).
Where are connected these signals? In schematics at pages 495-499 there's no sign of them.

How should I configure them?

 

• CCM_ENET1_REF_CLK / CCM_ENET2_REF_CLK / CCM_ENET3_REF_CLK

These signals appear to be output only to me. Could you confirm this?

Where are connected these signals? In schematics at pages 495-499 there's no sign of them.

I suppose they are derived from interbal signals ENET1_REF_CLK_ROOT or ENET2_REF_CLK_ROOT or ENET_PHY_REF_CLK_ROOT, but there's no explanation at all about this.

How should I configure them?

 

Thanks

Andrea

Labels (1)
0 Kudos
1 Solution
481 Views
art
NXP Employee
NXP Employee

1. The CLK1_P/N differential clock can be used as either input or output. Its function can be configured in the CCM_ANALOG_CLK_MISC0n register, please refer to the Section 5.2.9.18 of the i.MX7Solo Reference Manual document for details. When configured as output (LVDSCLK1_OBEN is set), it can take the clock form various on-chip sources, defined by the LVDS1_CLK_SEL field, and route it out of the chip. When configured as input ((LVDSCLK1_IBEN is set), it can take the clok from outside of the chip and then be used as the reference clock for the on-chip PLLs (to achieve this, the BYPASS bit of the corresponding CCM_ANALOG_PLL_XXXn register should be set and the BYPASS_CLK_SRC field should be set to 01). This input function of the CLK1_P/N differential signal is typically used for factory testing purposes and should not be used for normal operation.

CLK2 is the input only single-ended signal. It can be used as the external reference clock for the on-chip PLLs. For this, the BYPASS bit of the corresponding CCM_ANALOG_PLL_XXXn register should be set and the BYPASS_CLK_SRC field should be set to 10. This signal is typically used for factory testing purposes and should not be used for normal operation. Better is to connect this signal to ground in the end product.

2. CCM_ENET1_REF_CLK is the reference clock of the ENET1 module, derived from the ENET1_REF_CLK_ROOT clock, generated by the Clock Controller Module (CCM). It can be routed out of the chip through various IOMUX options, please refer to the IOMUX chapter of the reference manual for more details.

The same is for the ENET2 module CCM_ENET2_REF_CLK clock of i.MX7Dual. i.MX7Solo only has the CCM_ENET1_REF_CLK clock since it has only single ENET1 module.

CCM_ENET3_REF_CLK does not exist on either i.MX7Dual or i.MX7Solo processor, this is just the typo in the Reference Manual document.


Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
1 Reply
482 Views
art
NXP Employee
NXP Employee

1. The CLK1_P/N differential clock can be used as either input or output. Its function can be configured in the CCM_ANALOG_CLK_MISC0n register, please refer to the Section 5.2.9.18 of the i.MX7Solo Reference Manual document for details. When configured as output (LVDSCLK1_OBEN is set), it can take the clock form various on-chip sources, defined by the LVDS1_CLK_SEL field, and route it out of the chip. When configured as input ((LVDSCLK1_IBEN is set), it can take the clok from outside of the chip and then be used as the reference clock for the on-chip PLLs (to achieve this, the BYPASS bit of the corresponding CCM_ANALOG_PLL_XXXn register should be set and the BYPASS_CLK_SRC field should be set to 01). This input function of the CLK1_P/N differential signal is typically used for factory testing purposes and should not be used for normal operation.

CLK2 is the input only single-ended signal. It can be used as the external reference clock for the on-chip PLLs. For this, the BYPASS bit of the corresponding CCM_ANALOG_PLL_XXXn register should be set and the BYPASS_CLK_SRC field should be set to 10. This signal is typically used for factory testing purposes and should not be used for normal operation. Better is to connect this signal to ground in the end product.

2. CCM_ENET1_REF_CLK is the reference clock of the ENET1 module, derived from the ENET1_REF_CLK_ROOT clock, generated by the Clock Controller Module (CCM). It can be routed out of the chip through various IOMUX options, please refer to the IOMUX chapter of the reference manual for more details.

The same is for the ENET2 module CCM_ENET2_REF_CLK clock of i.MX7Dual. i.MX7Solo only has the CCM_ENET1_REF_CLK clock since it has only single ENET1 module.

CCM_ENET3_REF_CLK does not exist on either i.MX7Dual or i.MX7Solo processor, this is just the typo in the Reference Manual document.


Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos