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I.MX6DQRM parallel display DI0_DISP_CLK signal level

Question asked by younggeun kim on Sep 20, 2018
Latest reply on Sep 21, 2018 by igorpadykov


Dear ALL

I test I.MX6DQRM Parallel Display in sabre board.

I have a problem in parallel display interface clock level.

DI0_DISP_CLK' hw signal level is just 0.8V, it has DC offset about 1.3V.

Almost every output signal is operating in 0V ~ 3.3V, but DI0_DISP_CLK output clock is 0.8V.

How can I get normal DI0_DISP_CLK output clock?

I want to get 108Mhz, 3.3V DI0_DISP_CLK parallel output clock.

What I have to set?

Plz help reply.....

Thanks..

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