Bank Selection Bits in DDR3

[qammarabbas]

Hi,
The attached picture is taken from the reference manual of T1042. The query here is why there are only 2 sub-bank selection bits shown on each chip (indicated in red)? In this example all 8 sub banks are being used, and for that to happen we need 3 sub-bank selection bits (indicated in red in DDR controller). Please let me know where is the 3rd bit? Thank you!

[ufedor]

You are right - the picture has to be corrected.

You can refer to the T1040RDB design files available here:

QorIQ T1040 Reference Design Board|NXP 

[qammarabbas]

Thank you ufedor‌!
But i found this to be correct. The reason being in this diagram, each SDRAM device is of 64Mbits and according to the datasheet of 64Mbits SDRAM device it can only support 4 internal(logical) banks, therefore it will use only 2 bits instead of 3 for sub-bank selection.