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ADC sampling rate

Question asked by ulrik kristiansen on Jun 20, 2017
Latest reply on Jun 22, 2017 by Robin_Shen

Hi, I tried to follow up on a old question "", but I didn't get any answers, so now I am raising my own thread.


Based on the K24 Kinetis datasheet:

I do not understand, how a sample rate of 461.467 ksps is reachable with a ADC clock limited to 12 MHz. Don't you need 34 adc_clks + 5 adc_clks + 5 bus_clks = 39 adc_clks + 5 bus_clks?


Also, I do see sources talking about high clock frequency than 18 MHz (<= 13 bit mode). E.g. in this example for the same K24 Kinetis datasheet:


Please, would someone tell me how the 461.467 ksps sample rate is reachable and at which ADC clock?


Thanks, Ulrik