AnsweredAssumed Answered

Clarifications needed for MEMU development

Question asked by santhosh kumar on Mar 18, 2017
Latest reply on Mar 22, 2017 by santhosh kumar

Hi,

This is Santhosh Kumar, Technical leader, Delphi automotive systems, Bangalore, India.

 

For a Advanced Development Project in Power Train Division, We  use MPC5744 micro. And presently, am developing the device driver for MEMORY ERROR MANAGEMENT UNIT.

 

I request your support on this assignment.. My doubts are as under.

 

1. Where i can find the error sources which create the error ( correctable/uncorrectable)  for each memory section

( SYSTEM RAM/ PERIPHERAL RAM/FLASH). It  is told in the ref. manual that to refer the device configuration section.

We do have chip configuration section (Chapter 7) in reference manual . In that a table is given ( Section reference 7.11.2.1)with error sources which is respective for overflow status. Is these are the total error sources  for MPC5744..? or these error sources are only those which are responsible for Overflow status stamping..?

 

2. It is told that the REPORTING TABLE is accessible by the software (Section 68.7.2) . But , i could not able to find that the reporting table is memory mapped..? How to access the reporting table.

 

 Or My doubt is " if we write into the particular status & address register of a particular Memory section and setting the Valid bit " will make the written value with the Bad BIT and the VLD  to get reflected in the reporting table. 

 

3.There are 5 steps given to write the error  the error occurred address with the bad bit/syndrome   by the software ( Section 68.7.1). Could you please help me on understanding the 4 th and  5 step..?

 My doubt is it is said that at the s 5th step " Write address/bad bit information to desired address. ".May i get the clarity over the term "desired address".. 

  

4. In the memory Map,

 

   For system RAM, 10 sets of  correctable status register & address register    AND   1 set of uncorrectable status register    with address register AND  3 overflow registers are allocated.

 

  For Peripheral RAM,  sets of  correctable status register & address register    AND   1 set of uncorrectable status register    with address register AND  1 overflow registers are allocated.

 

    For Flash,  20 sets of  correctable status register & address register    AND   1 set of uncorrectable status register    with    address register AND  1 overflow registers are allocated.

 

   Is all these registers are applicable to MPC5744 ?

 

 It is said that to refer the "Device configuration section for better clarity for the respective and applicable register" . But i  could not find the answer for the above query in Chip configuration section . Could u please help me..?

 

 Overall, i  need to know the number of error sources for the each Memory section, and how it is related to the sets of  status and the address register and how it is written in the reporting table.. and how to access the reporting table.

 

 

If there is an availability of application note and the relative documents , request you to share with me. 

 

 

 

Expecting your guidance & reply  soon

Outcomes