Clarifications needed for MEMU development

[santoshkumar_n]

Hi,

This is Santhosh Kumar, Technical leader, Delphi automotive systems, Bangalore, India.

For a Advanced Development Project in Power Train Division, We  use MPC5744 micro. And presently, am developing the device driver for MEMORY ERROR MANAGEMENT UNIT.

I request your support on this assignment.. My doubts are as under.

1. Where i can find the error sources which create the error ( correctable/uncorrectable)  for each memory section

( SYSTEM RAM/ PERIPHERAL RAM/FLASH). It  is told in the ref. manual that to refer the device configuration section.

We do have chip configuration section (Chapter 7) in reference manual . In that a table is given ( Section reference 7.11.2.1)with error sources which is respective for overflow status. Is these are the total error sources  for MPC5744..? or these error sources are only those which are responsible for Overflow status stamping..?

2. It is told that the REPORTING TABLE is accessible by the software (Section 68.7.2) . But , i could not able to find that the reporting table is memory mapped..? How to access the reporting table.

 Or My doubt is " if we write into the particular status & address register of a particular Memory section and setting the Valid bit " will make the written value with the Bad BIT and the VLD  to get reflected in the reporting table. 

3.There are 5 steps given to write the error  the error occurred address with the bad bit/syndrome   by the software ( Section 68.7.1). Could you please help me on understanding the 4 th and  5 step..?

 My doubt is it is said that at the s 5th step " Write address/bad bit information to desired address. ".May i get the clarity over the term "desired address".. 

4. In the memory Map,

   For system RAM, 10 sets of  correctable status register & address register    AND   1 set of uncorrectable status register    with address register AND  3 overflow registers are allocated.

  For Peripheral RAM,  sets of  correctable status register & address register    AND   1 set of uncorrectable status register    with address register AND  1 overflow registers are allocated.

    For Flash,  20 sets of  correctable status register & address register    AND   1 set of uncorrectable status register    with    address register AND  1 overflow registers are allocated.

   Is all these registers are applicable to MPC5744 ?

 It is said that to refer the "Device configuration section for better clarity for the respective and applicable register" . But i  could not find the answer for the above query in Chip configuration section . Could u please help me..?

 Overall, i  need to know the number of error sources for the each Memory section, and how it is related to the sets of  status and the address register and how it is written in the reporting table.. and how to access the reporting table.

If there is an availability of application note and the relative documents , request you to share with me. 

Expecting your guidance & reply  soon

[xiaofeiruan]

Hi, Santhosh

I'm Stefan, Auto AE in China, I jsut give my answer for those questions, someone may append it later.

（1）7.12.2.1 chapter only show “Error sources for Concurrent Overflow (OFLWn) registers”, the overflow occur When multiple errors are indicated from various sources at same instant, an Overflow can be indicated by the MEMU to the FCCU. Overflow can also be indicated if the reporting table entries are full and a new unique error is reported by the system.

As RM said, MEMU is used to collect and report error event of ECC logic used on 3 regions: system RAM, Peripheral RAM and Flash, the ECC event includes correctable error and uncorrectable error for each of the 3 regions.

You can see from the MEMU Memory map and register definition(68.6), MEMU_SYS_RAM_CERR_xx range from 0 to 9,  MEMU_PERIPH_RAM_CERR_xx range from 0 to 1，MEMU_FLASH_CERR_xx range from 0 to 19. If an ECC error occur in corresponding region, the address which have ECC error should be latched in MEMU registers.  

 (2) Regarding reporting table

The 68.7.2 chapter says “the software at any time can read the reporting table via the software programming Interface”.  As my understanding, the MEMU ADDR/STS/OFLW registers are actually the reporting table. The table in 68.7.2 is just a representation of these registers, make it seem like a table intuitively.

 (3)   The 5 steps is used in initializing MEMU(68.7.1),  it said“The software can program the table with known error addresses by setting the valid bit and storing the corresponding error address”, the purpose is to “CPU can program the known errors into the reporting table to avoid their re-reporting by MEMU”.

The reporting table can be modified by HW and SW.  By HW, reporting table is changed if an ECC error occur, and this process is independent without CPU involved. By SW, the user can write something into it.

For the step3 to step5, firstly it set VLD bit to make one entry in table is valid, then check the address that is written previously is still invalid, finally change the address to the known error addresses(desired address).

 (4)  Regarding the memory map

The entries number is as below:

Error Source                 Number of entries in correctable error reporting table         Number of entries in uncorrectable error reporting table
Flash (c55fmc)                                                     20                                                                             1
System RAM                                                        10                                                                             1
Peripheral RAM                                                    2                                                                               1

In 7.12.2.1, table 7-31 describes the detailed error sources, you can see the number of error sources is not matched with the number of report table entry, this is reasonable, they are not one-to-one mapping. As my understanding, a new error occur will be recorded in reporting table if there are available entry.

Some useful information about MEMU can be found in MPC5744P safety manual.

As our RM is not clear for some chapters, my understand is not 100% confident, need more verification.

[santoshkumar_n]

Thanks Ruan for u r quick reply and the answers.U r clarifications helped me to develop the module fatser. But as u said, escalate my request to u r high authorities to get better clarifications. The RM should have been better to explain the module at better angle.

Developed the device driver with the help of Support from NXP. Thanks to NXP. But still , much Mysteries are there in MEMU :smileywink:. Let it be.  Planning to find out one by one in functional testing.

Now, The point is 

1. MEMU can be tested from micro point  of view: By creating the Memory errors and made to sense by ECC ( error Correction Code) or MBIST ( Memory Built in function test) and the tester has to verify the result by reading the reporting table.

This Method is only way to test the "Error Buffer Overflow( EBO) and the Concurrent Overflow Register and the Overflow error Sources.

2. MEMU can be tested from User point of view: The Tester himself can write the Defectable address and bits in the respective reporting table status and address register and veriying the same. By this Error Status bit of respective memory Map can be checked.

I finished the Test 2 and the result seems to be satisfactory.

But i don't know how to start with Test 1. I need assistance from u r experts team to create Memory Faults/errors at the Various Memory Section ( System RAM, Peripheral RAM , FLASH) and the respective error created should be found out by ECC/MBIST such that the error address with the bad bit will be captured  by the MEMU and registered in the Reporting table.

Request you to help me out to test the above Scenario.

Expecting the reply soon.

[xiaofeiruan · Accepted solution]

Hi,  Santhosh

Happy to see your progress in developing MEMU!

Let's answer your question regarding Test1.Actually, we have an example code to show how to generate 1bit/2bits ECC error in desire flash address, please see attached file.  By over-programming the same address with different value may lead to different kind of ECC error. It's not easy to explain it,  Since MPC5744P has Decorated Storage Memory Controller (DSMC), which support atomic read-modify-write memory operations. You can refer to Chapter 34 for more information, if you don’t care about the mechanism, you can just use it. 

Additionally, do you know we have a community for Power Architecture MCU, in that there are many example code, just find the link as below.  

https://community.nxp.com/docs/DOC-329623

[santoshkumar_n]

Hi Ruan,

 Thanks for your speedy reply. U r information( Error injection code shared) would be much useful.  let me test and update u at the earliest

Thanks & Regards

Santhosh Kumar.N