I'm currently working on the QorIQ T1040 integrated Ethernet switch. Our desing differs significantly from the T1040RDB board (this one is using QSGMII). We want to connect switch ports with other CPUs and switches directly (i.e. without PHYs) over SGMII. I'm having problems making it work though.
As I understand the uio_seville.ko kernel driver is responsible for allowing userspace communication with the VSC9953 switch core. It is also responsible for initializing the SERDES part using vsc9953_mdio_write function calls. If I understand correctly vsc9953_mdio_write and vsc9953_mdio_read functions accesss the SGMII register space as described in 31.5 MDIO register spaces. If so, the driver is writing to MDIO_SGMII_IF_MODE, MDIO_SGMII_DEV_ABIL_SGMII, MDIO_SGMII_LINK_TMR_H, MDIO_SGMII_LINK_TMR_L and MDIO_SGMII_CR registers.
I wanted to double check if those registers are configured correctly. After running vsc9953_lynx_init I dumped all SGMII registers and it turned out that only the one at PHY address 0x4 gets configured. All other PHY and register addresses return 0x0. I am 100% sure that vsc9953_lynx_init performs vsc9953_mdio_write for all 8 ports.
I dumped the RCW to see if it is configured as I want:
Reset Configuration Word (RCW):
00000000: 080d000e 05000000 00000000 00000000
00000010: 89000002 00000812 fc027000 41000000
00000020: 00000000 00000000 00000000 0002a780
00000030: 00000000 80160a05 00000000 00000000
The bold value (0x89) corresponds to what we want ot use (see Figure 31-1. Supported SerDes Options).
Do you have any idea why the SERDES part is not configured properly? What is the connection between tbi-phy reg number and SERDES port?
I attached my l2switch device tree node and MDIO_SGMII* register dump for all ports.
We are using Vitesse/Microsemi switches in our other products so the question of modifying l2sw_bin is another matter. Right now I would like to know how the physical layer to the switch operates.
Original Attachment has been moved to: uio_seville.txt.zip