In i.MX6SoloX RGMII1_TX_CTL delay to AR8035 it is recommended to implement 1.75ns TX_CTL delay as PCB trace delay and the following NXP PCB photo is presented as an example:
But the reference for the SABRE Board (https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fproducts%2Fmicrocontrollers-and-processors%2… isn't contain data.
The RGMII2 TX traces in the LAY-27962_C.brd have the following lengths:
So actually the TXCLK is almost shortest trace in the RGMII2 TX group and no delay is implemented by the PCB clock trace.
How the recommended RGMII clock delays are implemented in the NXP reference boards/design?