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i.MX6SoloX RGMII TX_CTL delay

Question asked by Vadim Aleynikov on Sep 20, 2016
Latest reply on Oct 13, 2016 by Yuri Muhin

Hello.

In i.MX6SoloX RGMII1_TX_CTL delay to AR8035  it is recommended to implement 1.75ns TX_CTL delay as PCB trace delay and the following NXP PCB photo is presented as an example:

circuit-board-traces.jpg

 

But the reference for the SABRE Board (https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fproducts%2Fmicrocontrollers-and-processors%2… isn't contain data.

The RGMII2 TX traces in the LAY-27962_C.brd have  the following lengths:

RGMII2_TXCLK: 1762.4mil

RGMII_TXD3: 2068.05mil

RGMII2_TXD2: 1899.02mil

RGMII2_TX1: 1835.57mil

RGMII2_TXD0: 1778.63mil

RGMII2_TXEN: 1710.34mil.

So actually the TXCLK is almost shortest trace in the RGMII2 TX group and no delay is implemented by the PCB clock trace.

How the recommended RGMII clock delays are implemented in the NXP reference boards/design?

 

Best regards,

Vadim Aleynikov

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