I am looking at the power down sequence paragraph 3.7.3 of the MPC5553 data sheet and I would like to request clarification, to understand the power down sequence requirement.
In our application VRC33 is hardwired to GND.
VDD =1.5V and VDDSYN =3.3V
When I remove 5 VDC which generates the 3.3V and the 1.5V I get an output glitch on 10 different pins which are expected to stay low during power down.
These pins are ADDR13, ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, CS3, CS2, CS1 AND CS0.
When the unexpected low to high glitch occurs on these outputs the voltages are as follows:
VDD = 1.5V
5V = 3.3V
Should my VDDSYN be below 2.0V when we produce a RESET?