We have a custom board and SGTL500 chip .And for this we have programmed board with bare-metal not Linux .
As per discussed in the mentioned link , after power cycle we need to fill SGTL registers with default values .
In our environment ,When we try to write reg with defaults value that too fails.
We have use PLL with integer divisor and fractional divisor equal to 16 and 786 respectively.
SYS_FS = 8 KHz
Provided System main clock = 12 MHz,
What needs to be done to resolve this issue ?? Please let me know.
SGTL5000 registers are configured in the following order
|ANA_CTRL||0x122 (Headphone Unmute)|