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swapping of ddr3 data pins in controller end

Question asked by agxin j on Apr 22, 2015
Latest reply on Jun 12, 2015 by Quinn Dinh

Hello sir

             I had gone through the ddr3 guidlines by freescale I could'nt find any constrains on no of  layers for routing.I am using  freescale processor P2041 connected to a 5-16 bit micron chips (one chip 8-bit for ECC) there are some criss cross in  routing .can I swap the pin outs of the data in controller within the byte ,If swaping is done do I have to modify any thing in the software or straight away will it work even with swapping ,can I use multiple layers for routing the address lines (i.e)from processor to dram in one layer and from dram to termination in some other layer ?Is there any contrain for routing in the external layer ?can i use 4 layers to route the address lines? Please share your experience or problems or precautions  on Layout making for DDR3.

 

regards

AGXIN.J

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