swapping of ddr3 data pins in controller end

[jagxin]

Hello sir

             I had gone through the ddr3 guidlines by freescale I could'nt find any constrains on no of  layers for routing.I am using  freescale processor P2041 connected to a 5-16 bit micron chips (one chip 8-bit for ECC) there are some criss cross in  routing .can I swap the pin outs of the data in controller within the byte ,If swaping is done do I have to modify any thing in the software or straight away will it work even with swapping ,can I use multiple layers for routing the address lines (i.e)from processor to dram in one layer and from dram to termination in some other layer ?Is there any contrain for routing in the external layer ?can i use 4 layers to route the address lines? Please share your experience or problems or precautions  on Layout making for DDR3.

regards

AGXIN.J

[jagxin]

Hai sir

Thanks for your reply sir I started swapping witin th lanes at the controller end

regards

AGXIN.J

[jagxin]

Hai sir

         I have another query for you? can swapping can also be done from  both the  ends  end i.e (fixing MDQ Pins and swapping the pins at the dram end DQ )Fixing DQ pins and swapping at the controller end MDQ)?

i.e Fixing the controller pinouts as such without modifing and swaping the pins at the DRAM end

MDQ0-------DQ3

MDQ1-------DQ2

MDQ2-------DQ1

MDQ3-------DQ0

i.e Fixing the DRAM  pinouts as such without modifing and swaping the pins at the CONTROLLER end

MDQ3------DQ0

MDQ2------DQ1

MDQ1------DQ2

MDQ0------DQ3

will this differ from processor to processor or for all the processor It can be done?

Regards

AGXIN.J

[r8070z]

You can swap on any side.
From physical point of view swapping within byte lane should be possible on any processor. However I could not say that for any processors. But it is definetely true for all Freescale QorIQ with DDR2/DDR3 controller (like P2041)

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[jagxin]

hai sir

              Thanks for your reply ,can we swap address lines too I could'nt Find in any data sheet that it can be done,If It cannot be done why is it so ? please help me in understanding the difference between data and address swaping issues .

regards

AGXIN.J

[r8070z]

The address lines should not be swapped. Please see DDR3 device description, how it is configured over address lines.

[itsme]

I believe the byte lane can be swapped too, right?  For instance, Byte 3 to Byte 7 and vise versa.  Thx

[r8070z]

Yes you can swap the pin outs of the data in controller within the byte. It does not require to modify any thing in the software.

For Layout making for DDR3 there is Freescale application note AN3940

Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces

You can find it on any Freescale site page using AN3940 as keyword.

Also there is training material DDR3 Design Considerations for Printed Circuit Board (PCB) Applications on Freescale page

http://www.freescale.com/webapp/sps/site/training_information.jsp?code=WBNR_VFTF09_AN111

http://www.freescale.com/files/training_pdf/VFTF09_AN111.pdf

[jagxin]

Hello sir

              Thanks for your reply as well as the links you have shared to me It was very useful.  Does swapping of data pins with in byte lanes  in the controller will  create any issue in implemention  parity algorithms in ECC ?

[r8070z]

"swapping of data pins within byte lanes" I understand as connection swapping, f.e. instead of connection MDQ0 to DQ0 and MDQ3 to DQ3 we can connect MDQ0 to DQ3 and MDQ3 to DQ0. Where MDQ is controller pin name while DQ is SDRAM pin name. On its DQ pin SDRAM returns what the controller writes to it and nothing more. All bits in the byte lane are equivalent and controlled by the same DQM and DQS. So controller does not care which of 8 equivalent SDRAM cell keeps byte’s bit.