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How many WFI instructions are needed for entering Stop mode ?

Question asked by Aurélien Martin on Mar 12, 2015
Latest reply on Mar 13, 2015 by Stefan Agner



  I have some troubles understanding both the Reference Manual (among other documentations), and those forums (fora ?). Right now I'm focusing on getting in and out of (LP)STOP mode, so I'll ask here my questions on this subject, and suggest you to consider releasing something lke an application note to clarify the workings of such modes, for others.


1 - To enter one such mode, be it STOP or LPSTOPn, we need to execute a WFI instruction. More precisely, in section 14.3.4 (Wait mode) of the RM, we find :


Wait mode is entered when the GPC_LPMR register is configured for Wait mode and the WFI (Wait For Interrupt) instruction is executed on the core.


The core ? Which core ? And later :


WFI for an individual core can be executed and GPC_LPMR may not be configured to enter into chip Wait mode. In dual-core configurations, the application can configure WFI to put a single core into halt. Other peripherals can continue operating at the configured frequencies if GPC_LPMR is configured to 00b, i.e., Run mode.


Ok, so if I'm to configure GPC_LPMR as 10b (STOP mode), and make any core execute WFI, I stall them both ? Then in CCM registers' description, we find :


M_CORE0_WFI : Mask WFI of core0 for entering low power mode

0 WFI of core0 is not masked

1 WFI of core0 is masked


And others of that ilk, for Core1 WFI, SCU Idle, and L2CC Idle. Please what does "mask" mean, here ? Do I get to mask one core's WFI, and so not fall into STOP mode when it occurs ? Or is it so that I actually need both WFI, simultaneously, to enter STOP mode (as suggested here), and that masking one would permit me to make do without it, and thus with only one core WFIing ? Actually, right now I'm more a believer of the second solution, according to the note just above those bits' description :

Setting all the bits CCM_CLPCR[M_CORE0_WFI], CCM_CLPCR[M_CORE1_WFI], CCM_CLPCR[M_SCU_IDLE], and Chapter 10 Clock Controller Module (CCM) Vybrid Reference Manual, Rev. 5, 07/2013 Freescale Semiconductor, Inc. 657 CCM_CLPCR[M_L2CC_IDLE] will result in stop mode or low power stop mode depending upon GPC.


But I really would appreciate some certainty.


2 - In LPSTOPn mode, power is gated for almost every module, including IOMUXC and GPIO. Does it mean that the Vybrid loses control of all its outputs ? That's certainly what I'm experiencing, but then again, I'm not quite sure of actually having reached LPSTOPnmode (see point 3, and point 1 for that matter). If that is so, do I have to pull down the CKE signal of the SDRAM bus, to allow selfrefresh to continue while the controller sleeps ? But this signal is pulled up on the TWR, is it and functional requirement ? So do I need to come up with some hardware trick to switch between pullup and pulldown depending on the state of my IOs ?


3 - When I try to go into LPSTOP2 mode (managing only the A5 core, with a vanilla Linux 3.19-rc4-XX), then to get out of it, what I experience is a software reset (ie. call of SRC_GPR0(SRC_GPR1). Is that the expected way out ? Or did I mess up somewhere ? For STOP mode or for LPSTOPn mode, am I supposed to continue execution after the WFI instruction, on wakeup, or to jump at [SRC_GPR0] ?


Thank you for your lights,


Aurélien Martin