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About i.MX6DQ clock tree

Question asked by Keita Nagashima on Jan 6, 2015
Latest reply on Feb 10, 2015 by igorpadykov

Dear Sir or Madam,

 

Hello.

I checked all PLLs value in MCIMX6DQRM(Rev.2) and found typo.

PLL4 and PLL5 looked 650MHz from "10.3.2.3 PLLs".

But, there were description of PLL4 and PLL5 = 630MHz in "Figure 18-2. Clock Tree".

Is this typo?

And, is there another typo in Figure 18-2?

 

Best Regards,

Keita

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