Dear Sir or Madam,
I checked all PLLs value in MCIMX6DQRM(Rev.2) and found typo.
PLL4 and PLL5 looked 650MHz from "10.3.2.3 PLLs".
But, there were description of PLL4 and PLL5 = 630MHz in "Figure 18-2. Clock Tree".
Is this typo?
And, is there another typo in Figure 18-2?