Dear Sir or Madam,
Hello.
I checked all PLLs value in MCIMX6DQRM(Rev.2) and found typo.
PLL4 and PLL5 looked 650MHz from "10.3.2.3 PLLs".
But, there were description of PLL4 and PLL5 = 630MHz in "Figure 18-2. Clock Tree".
Is this typo?
And, is there another typo in Figure 18-2?
Best Regards,
Keita
Solved! Go to Solution.
Hi Keita
recommended for usage 650MHz as lower limit, this is specified by
datasheet IMX6SDLCEC Table 15. Audio/Video PLL’s Electrical Parameters
though in theory it can be programmed down to 630MHz.
Best regards
igor
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Hi Keita
recommended for usage 650MHz as lower limit, this is specified by
datasheet IMX6SDLCEC Table 15. Audio/Video PLL’s Electrical Parameters
though in theory it can be programmed down to 630MHz.
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Dear Igor,
Hello.
Thank you for your reply.
OK. I got it.
But, below description looks typo.
Refer to NOTE of "18.3 CCM Clock Tree" in MCIMX6DQRM (Rev.2)
======
The default frequency values (in MHz) for the PLLs and PFDs
is the maximum allowed frequency. The PLL and PFD control
registers should not be programmed to exceed these values.
======
Could you request your document team to fix the typo?
Best Regards,
Keita
Hi Keita
I created SR-1-3572489011 for Doc team.
Best regards
igor
Dear Igor,
Hello.
Thank you for your support!
Is this SR number 1-3572489011 FSL's internal community?
I couldn't find it.
Best Regards,
Keita
Hi Keita
it is CRM number, you can ask local FAE
for tracking it.
Best regards
igor
Dear Igor,
OK. I understood it!
Thank you very much.
Best Regards,
Keita
Hi Keita
for that request internally I got next answer:
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Submitted Docs CT: 46474301
The note
"The default frequency values (in MHz) for the PLLs and PFDs is the maximum allowed frequency. The PLL and PFD control registers should not be programmed to exceed these values."
will be changed to
"The default frequency values (in MHz) for the PLLs and PFDs are shown in the Clock Tree diagram that follows. The PLLs and PFDs control registers may be reprogrammed according to the speed grade of the SoC being used, but should not exceed that maximum setting for that speed grade."
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Best regards
igor