Hi Keita
for that request internally I got next answer:
-------------------------------------------
Submitted Docs CT: 46474301
The note
"The default frequency values (in MHz) for the PLLs and PFDs is the maximum allowed frequency. The PLL and PFD control registers should not be programmed to exceed these values."
will be changed to
"The default frequency values (in MHz) for the PLLs and PFDs are shown in the Clock Tree diagram that follows. The PLLs and PFDs control registers may be reprogrammed according to the speed grade of the SoC being used, but should not exceed that maximum setting for that speed grade."
------------------------------------------
Best regards
igor