SabreSD SPI Driver Queries

[Shweta2015]

Hi All,

I have few queries related to the SPI driver on SabreSD board. I am using Ltib on kernel 3.0. I have to configure few ICs using  ECSPI1.(The SPI is same but the ICs will be selected using Chip Select pin). My queries are as follows:

1.     Should I use "spidev" for configuration? After changing .modalias in board-mx6q_sabresd.c, I was able to see spidev0.0 in the /dev file structure. But if i change .bus_num or .chip_select to value other than 0, i am not getting any spidev node in /dev. Should i be really changing it if I am using only ECSPI1 (does .bus_num = 0 correspond to ECSPI1)?

2.     How to configure the chip selects? From what i have read, I need to configure the Chip select pins as GPIO. In the board-mx6q_sabresd.c there is one configuration given as:

       #define   SABRESD_ECSPI1_CS0     IMX_GPIO_NR(4, 9)

     So, for the other two Chip Selects should it be something like:

     #define SABRESD_ECSPI1_CS2   IMX_GPIO_NR(3, 24)        //  ECSPI1_CS2 is at pad EIM_D24   

     #define SABRESD_ECSPI1_CS1   IMX_GPIO_NR(5, 9)          //  ECSPI1_CS1 is at pad DISP0_DAT15

3.  Along with the above modification I have done following changes, but still no luck:

static int mx6q_sabresd_spi_cs1[] = {

    SABRESD_ECSPI1_CS1,

};

static int mx6q_sabresd_spi_cs2[] = {

    SABRESD_ECSPI1_CS2,

};

static const struct spi_imx_master mx6q_sabresd_spi_data1 __initconst = {

    .chipselect     = mx6q_sabresd_spi_cs1,

    .num_chipselect = ARRAY_SIZE(mx6q_sabresd_spi_cs1),

};

static const struct spi_imx_master mx6q_sabresd_spi_data2 __initconst = {

    .chipselect     = mx6q_sabresd_spi_cs2,

    .num_chipselect = ARRAY_SIZE(mx6q_sabresd_spi_cs2),

};

static void __init mx6_sabresd_board_init(void)

{

-------

-------

     imx6q_add_ecspi(0, &mx6q_sabresd_spi_data1); 

     imx6q_add_ecspi(0, &mx6q_sabresd_spi_data2);

------

------

}

Still nothing. I need to know if my thinking is correct here or not? How can i configure the ICs using SPI. Is there any documentation which can be referred? Should I get different spidev (like spidev1.0, spidev1.1 etc.) to configure the different ICs.?

Thanks.

[alejandrolozan1]

Hi,

Have you checked this:

iMX53QSB cspi spidev configuration

The customer was able to register the spidev nodes under dev.

The iomux needs to be configured too.

Regards,

Alejandro

[Shweta2015]

Hi Alejandro,

Thank you for the reply. I have been able to get the device nodes for spidev1.0 and spidev1.1 under /dev by doing something like:

static int mx6q_sabresd_spi_cs1[] = {

    SABRESD_ECSPI1_CS1,

    SABRESD_ECSPI1_CS2,

};

But i still understand the IOMUXing macro:

#define SABRESD_ECSPI1_CS0    IMX_GPIO_NR(4, 9)

How is this configuration done? If I need to have configuration for ECSPI1_CS1, how can that be done, and what is the logic behind this macro definition?

Thanks.

[jaymind]

Hi Shweta,

#define SABRESD_ECSPI1_CS0    IMX_GPIO_NR(4, 9)

it means the CS0 of SPI1 is connected to pin no. 105 of i.MX6 :smileyhappy: and for programming or coding purpose this only number will useful and also system understand this number only to communication with the CS0 of SPI1 while programming.

IMX_GPIO_NR(4,9)

here 4 indicates the bank number and 9 indicates the bit number, now from below simple formula you can derive the actual hardware pin no., and from this pin no. you have to check your SOM board's  schematic or diagram whatever you have and then you will find the connector or actual hardware pin on main board.

The number of a GPIO is determined by formula :

(bank no. -1) * 32 + bit number

for your case it is 105 GPIO pin no.,

For help of this pin no. you will fin the CS0 pin on hardware connector where it OUT on connector.

Hope this will help you

Regards

JAYMIN D

[Shweta2015]

Hi Jaymin,

Thanks for the reply. I have gone though this formula and calculated the 105 value pin number, but I am not able to map it with the data sheet pin number. In the imx6 data sheet, only ball numbers are mentioned and for GPIO4_IO09, the ball number is U6. How does this correspond to 105 pin number (105 number is not given anywhere) ? If say, my ECSPI1_SS2 is on pad EIM_D24, how can I define its IMX_GPIO_NR macro?

Also, according to the reference manual the default mode set is ALT5 for KEY_ROW1 pad which corresponds to GPIO4_IO09 signal. For setting it to ECSPI1_CS0 signal we need to change the mode to ALT0, where can that be achieved? I got some clue by looking into the file, board-mx6q_sabresd.h, where MX6Q_PAD_KEY_ROW1__GPIO_4_9 has been given, but I feel that it should have been MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 instead for ECSPI1, chip select0. Totally confused here.

Thanks.

[jaymind]

Hi Shweta,,

1st thing that the user manual is 5,800 something page approx., hope you referring correct one. :smileycheck:

and if it is correct you have then go to page no. 2087 and topic no. 36.4.125Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1) and page no.

2653 topic no. 36.4.507Select Input Register (IOMUXC_ECSPI1_SS0_SELECT_INPUT) on wards.find for this name in document "IOMUXC_ECSPI1_SS0_SELECT_INPUT field descriptions" and "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 field descriptions"

as per the table the value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 should be 0x0000 for ALT0 — Select signal ECSPI1_SS0 as I think.

I will give you more input regarding to its soon,

Please check it and please find out iomuxreg file in your source directory where we can change the value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 reg.

This will help you.

Regards

JAYMIN D