Hi Qiang,
You're right about the spidev node. I added two spidev nodes, and now I can open both /dev/spidev0.0 and /dev/spidev0.1.
I tried mxc_spi_test1 and it works.
Now I ran into a different problem (or possibly two different problems).
The first chip select signal ECSPI1_SS0) seems to work although it works in a strange way. It goes low for every byte sent on the SPI bus. If I send 4 bytes it goes low and back high 4 times. I think it should go low and stay low for the entire transfer (all 4 bytes).
In the imx6 Reference Manual I found 21.4.4.1, Typical Master Mode. The diagram in that chapter is what I thought the SS signal should look like. Do I have to do something to set the controller in that mode?
The second chip select signal doesn't work at all. It doesn't go low when I send data to /dev/spidev0.1. The clock and the mosi lines wiggle as they're supposed to.
Here are the changes that I've made to the device tree:
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index b476518..7929bad 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -40,3 +40,40 @@
&epdc {
status = "disabled";
};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <2>;
+ /* cs-gpios = <&gpio3 12 0>, <&gpio3 27 0>; */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1_1>;
+ status = "okay";
+
+ spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <20000000>;
+ };
+ spidev@1 {
+ compatible = "spidev";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+#if 0
+&ecspi2 {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+};
+
+&ecspi4 {
+ status = "okay";
+};
+#endif
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 95bd7b1..5b5ded2 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -32,6 +32,10 @@
serial4 = &uart5;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
};
intc: interrupt-controller@00a01000 {
@@ -1083,6 +1087,8 @@
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x100b1
+ MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x100b1
>;
};
Thanks.