I.MX 6SoloX (Single step debug M4)

[tcmichals]

According to Chapter 13 the ETM trace buffer and Trace port are accessible from the ARM Cortex A9, but how about single single step registers?  i.e I'm trying to some how debug the ARM M4 via the ARM 9.  So, no external debug SWD HW is required.  is it possible?

[alejandrolozan1]

Hi Tim,

I am not an expert in the debug system but this statement in the RM makes me think it is possible.

Internal access to on-chip buses and other interfaces are provided by the access ports

(APs). The available APs are:

• AHB-AP which provides an AHB-Lite master for access to a system AHB bus.

• APB-AP which provides an AMBA 3 APB master for access to the Debug APB that

configures all CoreSight components.

• JTAG-AP which provides JTAG access to on-chip components and operates as a

JTAG master port to drive JTAG chains throughout the chip.

As far as I know the ETM trace buffer is just iRAM used for trace and therefore it can be accessed by both cores.

Let me keep delving into this.

Best Regards,

Alejandro

[tcmichals]

Alejandro,

Thank you for looking into this. I agree about the trace buffer. The goal is to create a simple gdb-server to access the HW debug registers directly, nmap the memory to user space.

(Wish I could get a sabre board to try this on :smileywink:)

[alejandrolozan1]

Other solution, maybe not an elegant solution is the next.

I have seen a few MCUs used as JTAG programmers, that use an SPI port.  You could try to create your firmware and use the SPI module and hook connect the corresponding signals to the JTAG interface.

/Regards,

Alejandro