i.mx6 Linux CPU IRQ affinity

[benanderson]

I am trying to test out the IRQ handling on the imx6. I was trying to change the affinity of the IRQ I am using in my driver. It seems like I am not able to it for some reason.

Does anyone know if IRQ affinity is supported under Linux for the ARM and the i.mx6?

Here is what I have tried.

Here is the output of /proc/interrupts showing that all the interrupts on system end up on cpu0.

root@freescale /proc/irq$ cat /proc/interrupts

            CPU0       CPU1       CPU2       CPU3

  34:          1          0          0          0       GIC sdma

  35:          0          0          0          0       GIC VPU_JPG_IRQ

  37:          0          0          0          0       GIC imx-ipuv3

  38:          0          0          0          0       GIC imx-ipuv3

  39:          0          0          0          0       GIC imx-ipuv3

  40:          0          0          0          0       GIC imx-ipuv3

  44:          0          0          0          0       GIC VPU_CODEC_IRQ

  51:          0          0          0          0       GIC snvs_rtc

  56:         48          0          0          0       GIC mmc1

  57:          0          0          0          0       GIC mmc0

  59:       1832          0          0          0       GIC IMX-uart

  63:          4          0          0          0       GIC spi_imx

  68:        468          0          0          0       GIC imx-i2c

  69:          0          0          0          0       GIC imx-i2c

  70:          1          0          0          0       GIC imx-i2c

  72:         25          0          0          0       GIC usb_wakeup

  75:          0          0          0          0       GIC usb_wakeup

  82:          0          0          0          0       GIC asrc

  87:     248984          0          0          0       GIC i.MX Timer Tick

121:          0          0          0          0       GIC dvfs

150:      12449          0          0          0       GIC fec

292:          0          0          0          0      GPIO itest

294:          0          0          0          0      GPIO mmc0

448:          0          0          0          0      GPIO mmc1

I tried to change the affinity using the /proc/irq/IRQ#/ files.  My interrupts is number 292 (itest).

root@freescale /proc/irq/292$ ls

affinity_hint node smp_affinity_list

itest smp_affinity spurious

Here is the current affinity which shows that the IRQ can be on any CPU. Output is suppose to be bit mask of each CPU. So 0xF sets the affinity

for each of the four CPUs.

root@freescale /proc/irq/292$ cat smp_affinity

f

If I try and set it nothing changes.

root@freescale /proc/irq/292$ echo 0x2 > smp_affinity

root@freescale /proc/irq/292$ cat smp_affinity

f

Here is link to kernel doc describing the /proc/irq (irq smp affinity) interface.

http://lxr.linux.no/linux+v3.0.15/Documentation/IRQ-affinity.txt

I tried figuring out if I was missing a kernel configuration option and can't find anything. There is an AUTO_IRQ_AFFINITY config option when I search in the menuconfig but doesn't seem to be any way to change the setting and it doesn't seem dependent on anything. I am not even sure that is what I need. I see what appears to be IRQ affinity code in the /arch/arm but it isn't clear to me.

Thanks,

Ben

[weiping_liu · Accepted solution]

Hi ben ,

   Because the irq is internal IRQ when it's number more than 255, so you can't set affinity.

In addition , the command is "echo 2 > smp_affinity", not  "echo 0x2 > smp_affinity"

for example:

root@freescale ~$ cd /proc/irq/35
root@freescale /proc/irq/35$ cat smp_affinity
f
root@freescale /proc/irq/35$ echo 2 > smp_affinity
root@freescale /proc/irq/35$ cat smp_affinity
2
root@freescale /proc/irq/35$

You can reference the code in gic.c.

[benanderson]

Weiping Liu is correct however I am then stuck with needing a gpio that I can use as an interrupt that can also have its cpu affinity changed.  From the freescale imx6 documentation it list several gpio interrupts within the 255 limit.  However I could not find any indication in the GPIO chapter how the GPIO1 is configured to deliver these interrupts.

The gpio_to_irq macro translates the gpio bank and number and adds 255 to it.  Which makes sense given my gpio irq.

(gpio bank 2 number 4) ==> 256+32+4 ==> 292

I was able to request_irq() IRQ number 90 but have know idea what the source of the irq is other then GPIO1 and that it is called INT7. 

Here is the list of gpio interrupts below the 255 (from imx6 docs)

90 GPIO1 INT7 interrupt request.

91 GPIO1 INT6 interrupt request.

92 GPIO1 INT5 interrupt request.

93 GPIO1 INT4 interrupt request.

94 GPIO1 INT3 interrupt request.

95 GPIO1 INT2 interrupt request.

96 GPIO1 INT1 interrupt request.

97 GPIO1 INT0 interrupt request.

98 GPIO1 Combined interrupt indication for GPIO1 signals 0 - 15.

99 GPIO1 Combined interrupt indication for GPIO1 signals 16 - 31.

100 GPIO2 Combined interrupt indication for GPIO2 signals 0 - 15.

101 GPIO2 Combined interrupt indication for GPIO2 signals 16 - 31.

102 GPIO3 Combined interrupt indication for GPIO3 signals 0 - 15.

103 GPIO3 Combined interrupt indication for GPIO3 signals 16 - 31.

104 GPIO4 Combined interrupt indication for GPIO4 signals 0 - 15.

105 GPIO4 Combined interrupt indication for GPIO4 signals 16 - 31.

106 GPIO5 Combined interrupt indication for GPIO5 signals 0 - 15.

107 GPIO5 Combined interrupt indication for GPIO5 signals 16 - 31.

108 GPIO6 Combined interrupt indication for GPIO6 signals 0 - 15.

109 GPIO6 Combined interrupt indication for GPIO6 signals 16 - 31.

110 GPIO7 Combined interrupt indication for GPIO7 signals 0 - 15.

111 GPIO7 Combined interrupt indication for GPIO7 signals 16 - 31.

I also see that in mx6.h I have the following.  Which matches up with documentation.

#define MXC_INT_GPIO1_INT7_NUM		90
#define MXC_INT_GPIO1_INT6_NUM		91
#define MXC_INT_GPIO1_INT5_NUM		92
#define MXC_INT_GPIO1_INT4_NUM		93
#define MXC_INT_GPIO1_INT3_NUM		94
#define MXC_INT_GPIO1_INT2_NUM		95
#define MXC_INT_GPIO1_INT1_NUM		96
#define MXC_INT_GPIO1_INT0_NUM		97
#define MXC_INT_GPIO1_INT15_0_NUM	98
#define MXC_INT_GPIO1_INT31_16_NUM	99
#define MXC_INT_GPIO2_INT15_0_NUM	100
#define MXC_INT_GPIO2_INT31_16_NUM	101
#define MXC_INT_GPIO3_INT15_0_NUM	102
#define MXC_INT_GPIO3_INT31_16_NUM	103
#define MXC_INT_GPIO4_INT15_0_NUM	104
#define MXC_INT_GPIO4_INT31_16_NUM	105
#define MXC_INT_GPIO5_INT15_0_NUM	106
#define MXC_INT_GPIO5_INT31_16_NUM	107
#define MXC_INT_GPIO6_INT15_0_NUM	108
#define MXC_INT_GPIO6_INT31_16_NUM	109
#define MXC_INT_GPIO7_INT15_0_NUM	110
#define MXC_INT_GPIO7_INT31_16_NUM	111

Is there somewhere I can get more information or does someone have examples on how to use these gpio irqs? 

Ben Anderson

[fangxu]

Re: bind a gpio interrupt to cpu2