RT1050 Temperature Monitor Panic Temperature

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RT1050 Temperature Monitor Panic Temperature

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michaelsmorto
Contributor IV

I have been working with SDK example for temperature monitoring and now working on a barebones version.  I have a few questions on what happens when the Panic Temperature Threshold is breached.

  1. According to the manual when the Panic Alarm is tripped the IRQ panic bit should be set in CCM_ANALOG_MISC1 register and looks like in the PMU_MISC1 register as well.  Bit is 27 according to the reference manual.  Am I correct so far.  If I am then this bit never seems to get set only the High Temp alarm bit gets set.
  2. Then from what I understand if the panic bit gets set it should trip a system reset with the SRC_SRSR bit 8 indicating that the system was reset due to the temperature.

So I guess what this question boils down to is why the panic bit is never getting set and the system doesn't reset.  Also, if you have an example of how this should work can you please share.

Respectfully and happy new year.

Mike

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Michael Smorto,

Thanks for your reply.
I've attached a correct struct which illustrates the TEMPMON Memory Map below, please check it.

/*!
 * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
 * @{
 */

/** TEMPMON - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[384];
  __IO uint32_t TEMPSENSE0;                        /**< Tempsensor Control Register 0, offset: 0x180 */
  __IO uint32_t TEMPSENSE0_SET;                    /**< Tempsensor Control Register 0, offset: 0x184 */
  __IO uint32_t TEMPSENSE0_CLR;                    /**< Tempsensor Control Register 0, offset: 0x188 */
  __IO uint32_t TEMPSENSE0_TOG;                    /**< Tempsensor Control Register 0, offset: 0x18C */
  __IO uint32_t TEMPSENSE1;                        /**< Tempsensor Control Register 1, offset: 0x190 */
  __IO uint32_t TEMPSENSE1_SET;                    /**< Tempsensor Control Register 1, offset: 0x194 */
  __IO uint32_t TEMPSENSE1_CLR;                    /**< Tempsensor Control Register 1, offset: 0x198 */
  __IO uint32_t TEMPSENSE1_TOG;                    /**< Tempsensor Control Register 1, offset: 0x19C */
       uint8_t RESERVED_1[240];
  __IO uint32_t TEMPSENSE2;                        /**< Tempsensor Control Register 2, offset: 0x290 */
  __IO uint32_t TEMPSENSE2_SET;                    /**< Tempsensor Control Register 2, offset: 0x294 */
  __IO uint32_t TEMPSENSE2_CLR;                    /**< Tempsensor Control Register 2, offset: 0x298 */
  __IO uint32_t TEMPSENSE2_TOG;                    /**< Tempsensor Control Register 2, offset: 0x29C */
} TEMPMON_Type;



/* TEMPMON - Peripheral instance base addresses */
/** Peripheral TEMPMON base address */
#define TEMPMON_BASE                             (0x400D8000u)
/** Peripheral TEMPMON base pointer */
#define TEMPMON                                  ((TEMPMON_Type *)TEMPMON_BASE)
/** Array initializer of TEMPMON peripheral base addresses */
#define TEMPMON_BASE_ADDRS                       { TEMPMON_BASE }
/** Array initializer of TEMPMON peripheral base pointers */
#define TEMPMON_BASE_PTRS                        { TEMPMON }‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍


Have a great day,
TIC

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Michael Smorto,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
In the SDK demo, it provides the TEMPMON_SetTempAlarm() function to allow the developer to enable the panic alarm mode, to implement this feature, it also needs the developer to emulate a high-temperature condition for testing.

/*!
 * brief Set the temperature count (raw sensor output) that will generate an alarm interrupt.
 *
 * param base TEMPMON base pointer
 * param tempVal The alarm temperature with degrees Celsius
 * param alarmMode The alarm mode.
 */
void TEMPMON_SetTempAlarm(TEMPMON_Type *base, uint32_t tempVal, tempmon_alarm_mode alarmMode)
{
    /* Check arguments */
    assert(NULL != base);

    uint32_t tempCodeVal;

    /* Calculate alarm temperature code value */
    tempCodeVal = (uint32_t)(s_hotCount + (s_hotTemp - tempVal) * s_roomC_hotC / s_hotT_ROOM);

    switch (alarmMode)
    {
        case kTEMPMON_HighAlarmMode:
            /* Set high alarm temperature code value */
            base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_ALARM_VALUE(tempCodeVal);
            break;

        case kTEMPMON_PanicAlarmMode:
            /* Set panic alarm temperature code value */
            base->TEMPSENSE2 |= TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(tempCodeVal);
            break;

        case kTEMPMON_LowAlarmMode:
            /* Set low alarm temperature code value */
            base->TEMPSENSE2 |= TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(tempCodeVal);
            break;

        default:
            assert(false);
            break;
    }
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍


Have a great day,
TIC

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michaelsmorto
Contributor IV

Hi JeremyZhou

Think you misunderstand the question and issue.  

I have used TEMPMON_SetTempAlarm to set the alarm thresholds.  I have also set the high and panic temps low enough to ensure the alarms levels would be tripped. 

This is what I see happening:

1. When the high temp alarm is tripped bit 29 (high temp) goes from Low to High for registers CCM_ANALOG_MISC1 and PMU_MISC1.

2. When the panic temp alarm should have been tripped the high temp bit in CCM_ANALOG_MISC1 and PMU_MISC1 remains high (1) but bit 27 (Panic bit) stays low (0).

From what I understand when the system sees the panic bit (27) go high (change from 0 to 1 (low to high))system should automatically reset.  This is not what is happening. So the question is why this is not happening or is there something else that needs to be done?

thanks

Mike

EDIT:  Just to let you know the sample temp monitor for the EVKB does work - the reset does occur.  But when I try and do the exact same thing in bare metal it does not.  When the panic temp is exceeded it does not reset.

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Michael Smorto,

Thanks for your clarification.
So you've modified the tempmon demo, it can work on the i.MX RT1050 board, however, it fails with your own board, does it right?
If yes, I was wondering if you can share the modified demo, and let me dig much deeper.
Have a great day,
TIC

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michaelsmorto
Contributor IV

Hi Jeremy

Actually, spent the day trying to debug the issue comparing results between the EVKB and my board with a lot print statements and the issue seems to be that the panic temperature is not being set correctly when I set the panic alarm, the high and low alarms are being set correctly.  Here are the results setting the panic alarm, so you can see what I mean:

   alarmMode 1 (Panic), Temp Code Val to be set: 1262 (Value for the panic alarm - this is correct)
   TEMPMON_TEMPSENSE2 on entry to function: 0   (Yep as it should be)
   PanicValue 0100111011100000000000000000  (= 1262 matches), from the same macro that is in the example sketch,    tried a couple of other formats as well with the same result (will probably change the way I am currently doing it with    the macro)
   TEMPMON_TEMPSENSE2: 111011100000000000000000  (Panic is set at 238? This is after I do the    tempmon_tempsense2 |= PanicValue
      However, 0 or'd with panic value should be 10011101110 0 000 000000000000, essentially the same as Panic value.

So i guess the question comes is why doesn't it get set correctly, and is just doing tempmon_tempsense2 |= PanicValue ok or should I be using the set register to be doing that?

Just for reference I am using the C++14 compiler on my board vs C++ I used on the EVKB.

Hope this gives you enough info, otherwise I can send you the .h/.cpp files

Thanks for the help.  Been working this one issue and its driving me crazy and can't figure out whats causing it.

Mike

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Michael Smorto,

Thanks for your reply.
It's okay to set the TEMPSENSE2 register directly as the below code illustrates.

       case kTEMPMON_PanicAlarmMode:
            /* Set panic alarm temperature code value */
            base->TEMPSENSE2 |= TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(tempCodeVal);
            break;‍‍‍‍

Have a great day,
TIC

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michaelsmorto
Contributor IV

Hi Jeremy

Finally tracked down the root cause of the issue - something real dumb

Had the address for TEMPSENSE2 Wrong!  Once corrected it resets with out an issue when the panic temp is tripped just like the sdk example.

Thanks for your help.

Mike

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Michael Smorto,

Thanks for your reply.
I've attached a correct struct which illustrates the TEMPMON Memory Map below, please check it.

/*!
 * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
 * @{
 */

/** TEMPMON - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[384];
  __IO uint32_t TEMPSENSE0;                        /**< Tempsensor Control Register 0, offset: 0x180 */
  __IO uint32_t TEMPSENSE0_SET;                    /**< Tempsensor Control Register 0, offset: 0x184 */
  __IO uint32_t TEMPSENSE0_CLR;                    /**< Tempsensor Control Register 0, offset: 0x188 */
  __IO uint32_t TEMPSENSE0_TOG;                    /**< Tempsensor Control Register 0, offset: 0x18C */
  __IO uint32_t TEMPSENSE1;                        /**< Tempsensor Control Register 1, offset: 0x190 */
  __IO uint32_t TEMPSENSE1_SET;                    /**< Tempsensor Control Register 1, offset: 0x194 */
  __IO uint32_t TEMPSENSE1_CLR;                    /**< Tempsensor Control Register 1, offset: 0x198 */
  __IO uint32_t TEMPSENSE1_TOG;                    /**< Tempsensor Control Register 1, offset: 0x19C */
       uint8_t RESERVED_1[240];
  __IO uint32_t TEMPSENSE2;                        /**< Tempsensor Control Register 2, offset: 0x290 */
  __IO uint32_t TEMPSENSE2_SET;                    /**< Tempsensor Control Register 2, offset: 0x294 */
  __IO uint32_t TEMPSENSE2_CLR;                    /**< Tempsensor Control Register 2, offset: 0x298 */
  __IO uint32_t TEMPSENSE2_TOG;                    /**< Tempsensor Control Register 2, offset: 0x29C */
} TEMPMON_Type;



/* TEMPMON - Peripheral instance base addresses */
/** Peripheral TEMPMON base address */
#define TEMPMON_BASE                             (0x400D8000u)
/** Peripheral TEMPMON base pointer */
#define TEMPMON                                  ((TEMPMON_Type *)TEMPMON_BASE)
/** Array initializer of TEMPMON peripheral base addresses */
#define TEMPMON_BASE_ADDRS                       { TEMPMON_BASE }
/** Array initializer of TEMPMON peripheral base pointers */
#define TEMPMON_BASE_PTRS                        { TEMPMON }‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍


Have a great day,
TIC

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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michaelsmorto
Contributor IV

Thanks for all your help.  I did check it and it was only TEMPSENSE2 that I had messed up.  

Mike

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