RT1050 LwIP examples need to modify?

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RT1050 LwIP examples need to modify?

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felix1
Contributor IV

continued on thread

https://community.nxp.com/t5/i-MX-RT/RT1050-ENET-INT-pin-direction/td-p/1773686

 

1) In example evkbimxrt1050_lwip_ping_freertos, except to change ENET_INT as input, what else should I do?

2) Where can I find example evkbimxrt1050_lwip_ping_freertos in the mcuxpresso github 

https://github.com/nxp-mcuxpresso/mcux-sdk/tree/main/boards/evkbimxrt1050 ?

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @felix1 ,

  Please check the PHY datasheet:

https://ww1.microchip.com/downloads/en/DeviceDoc/00002202C.pdf

page 46:

 

kerryzhou_0-1703491325479.png

You can find, if your VDDIO is 3.3V, the input High voltage min is 2.0 V, so your 1.65V is not enough.

You may need a voltage switch to change the voltage level.

Why you don't refer to the EVK board, the NVCC_GPIO is using the 3V3?

kerryzhou_1-1703491486490.png

 

If you do it like this, I think you can output 3.3V as the high level.

 

Wish it helps you!

Best Regards,

Kerry

 

 

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @felix1 ,

   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.

Answer your 2 questions:

1) In example evkbimxrt1050_lwip_ping_freertos, except to change ENET_INT as input, what else should I do?

=>Answer: If your ENET PHY design is the same as the NXP MIMXRT1050-EVKB, then you totally can refer to the SDK evkbimxrt1050_lwip_ping_freertos.

ENET_INT in fact is configured as the GPIO, and use the output.

except this, you also can find these code, for the RESET.

 

    gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};   
 GPIO_PinInit(GPIO1, 9, &gpio_config);
    GPIO_PinInit(GPIO1, 10, &gpio_config);
    /* Pull up the ENET_INT before RESET. */
    GPIO_WritePinOutput(GPIO1, 10, 1);
    GPIO_WritePinOutput(GPIO1, 9, 0);
    SDK_DelayAtLeastUs(10000, CLOCK_GetFreq(kCLOCK_CpuClk));
    GPIO_WritePinOutput(GPIO1, 9, 1);

 

IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9U);

IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9U);

2) Where can I find example evkbimxrt1050_lwip_ping_freertos in the mcuxpresso github 

https://github.com/nxp-mcuxpresso/mcux-sdk/tree/main/boards/evkbimxrt1050 ?

=>Answer: You can download the SDK demo from this area instead of the github:

https://mcuxpresso.nxp.com/en/builder?hw=EVKB-IMXRT1050

 

Wish it helps you!

Best Regards,

Kerry

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felix1
Contributor IV

Hi @kerryzhou ,

1) according to evkbimxrt1050_lwip_ping_freertos, it's configured as output, not input.

gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
GPIO_PinInit(GPIO1, 10, &gpio_config);

 

according to MultipleMonomials,

https://community.nxp.com/t5/i-MX-RT/RT1050-ENET-INT-pin-direction/m-p/1777457/emcs_t/S2h8ZW1haWx8dG...

ENET_INT pin first as output to disable NAND tree test mode, then can change to as input for PHY link status interrupt, but interrupt usage not show in the example.

Can you verify it?

2) I want to check the change history for evkbimxrt1050_lwip_ping_freertos, but NXP seems not push example in the github.

  

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @felix1 ,

1. Yes, the ENET_INT pin is used to configure as the output, output high to disable the NAND tree mode. 

kerryzhou_0-1703135039022.png

 

To the input interrupt function, I checked the code, it is not used this ENET_INT function in the code. So,didn't configure it.

If you need it, you can configure the GPIO as input, and add the related interrupt.

2. About the change log, you can refer to the SDK MCUXpresso SDK ChangeLog_MIMXRT1052.pdf in 

SDK_2_14_0_EVKB-IMXRT1050\docs

 

Wish it helps you!

Best Regards,

kerry

 

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felix1
Contributor IV

Hi @kerryzhou ,

My customer board ENET_INT pin use the same schematic as EVK, solder both the pull-up (R309, 1K) and pull-down (R152, 1K) resistors. The ENET_INT output is 1.65V to PHY, can it disable the PHY NAND tree mode successfully? If not, any problem will happen?

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @felix1 ,

   In fact, you just need to check your used PHY, whether 1.65V can be indicate as the high level, if yes, then it is OK.

 So, please check your used PHY datasheet about the high level situation.

Best Regards,

Kerry

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felix1
Contributor IV

Hi @kerryzhou,

I copy EVK's network schematic, the PHY KSZ8081RNB is the same as EVK, so I need to know the design of EVK's ethernet is stable or not?

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @felix1 ,

  Please check the PHY datasheet:

https://ww1.microchip.com/downloads/en/DeviceDoc/00002202C.pdf

page 46:

 

kerryzhou_0-1703491325479.png

You can find, if your VDDIO is 3.3V, the input High voltage min is 2.0 V, so your 1.65V is not enough.

You may need a voltage switch to change the voltage level.

Why you don't refer to the EVK board, the NVCC_GPIO is using the 3V3?

kerryzhou_1-1703491486490.png

 

If you do it like this, I think you can output 3.3V as the high level.

 

Wish it helps you!

Best Regards,

Kerry

 

 

 

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