iMX RT and S25FL512S do not work

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iMX RT and S25FL512S do not work

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hiro33
Contributor III

Hello

I developed Custom board using iMX RT 1064 and use S25FL512S external flash memory.

QuadSPI Write seems to be working. However, QuadSPI Read is not working.

Expect 0xFFFFFFFF -> but 0xEFFFFFFF most significant bit are 0.

Will the combination of iMX RT 1064 and S25FL512S work?

I write a LUT for reference. Is there anything wrong with it?

const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
/* Normal read mode -SDR */
[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x13, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Fast read mode - SDR */
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0C, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Fast read quad mode - SDR */
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x6C, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),

/* Read Identification - REMS */
[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x90, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x03),
[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Write Enable */
[4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Erase Sector */
[4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),

/* Page Program - single mode */
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x12, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Page Program - quad mode */
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x34, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Read ID */
[4 * NOR_CMD_LUT_SEQ_IDX_READID] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Enable Quad mode, Latency Code set */
[4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),

/* Read Configuration Register (RDCR 35h) */
[4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Exit QPI mode */ /* 使用しない。S25FL512SAGMFA010に無いコマンドだが共通化のため削除しない */
[4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Read status register */
[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Erase whole chip */
[4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
};

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 ,

   Glad to hear 0xEB works on your side, our side mainly use this as the fast read in the QSPI flash.

  About 3- or 4-byte address, I think you need to check your QSPI flash chip, in my memory, some QSPI should has one bit to select 3 or 4 bytes address.

  To your chip, I think you also need to check your datasheet.

  You also can try 0XEC, this is 4 byte address.

kerryzhou_0-1629858020313.png

 

Wish it helps you!

Best Regards,

Kerry

 

 

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 ,

    I checked your LUT, the command is correct.

    Now, in your customer board, which flexSPI detail pins you connect the external QSPI flash? Do you refer to MIMXRT1064-EVK board?

    BTW, what about the DQS pin, do you leave it as float or not?

   If your connection the same as the EVK board, then you can run this code:

SDK_2_10_0_EVK-MIMXRT1064\boards\evkmimxrt1064\driver_examples\flexspi\nor\polling_transfer

And use your modified LUT, BTW, check your QE bit postion, modify the flexspi_nor_enable_quad_mode as the correct writevalue.

 

Wish it helps you!

Best Regards,

Kerry

 

    

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hiro33
Contributor III

Hi Kerry!

Thank you for your answer.
I refer to MIMXRT1064-EVK board.

I use FlexSPI(not FlexSPI2).

Pin
SCK:GPIO_SD_B1_04
CS:GPIO_SD_B0_04
SI/IO0:GPIO_SD_B1_03
SO/IO1:GPIO_SD_B1_02
WP/IO2:GPIO_AD_B1_05
HOLD/IO3:GPIO_AD_B1_04

DQS uses a dummy signal for internal loopback.
I'm running the following code when using FlexSPI.

config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;


QE bit postion
QE bit position changed for S25FL512S,
It is set to bit1 = 1 of the Configuration Register.

config.PNG

 

 

 

 

 

#define FLEXSPI_CONFIG_REG_QUAD_SET_VALUE 0x82U //!< Latency Code = 2, QUAD = 1

status_t flexspi_nor_enable_quad_mode2(FLEXSPI_Type *base, flexspi_port_t st_port)
{
flexspi_transfer_t flashXfer;
status_t status;
uint32_t writeValue = 0x0200;
uint32_t configValue;

/*! Read Configuration Register */
flashXfer.deviceAddress = 0;
flashXfer.port = st_port;
flashXfer.cmdType = kFLEXSPI_Read;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ENTERQPI; //!< Read Configuration Register (RDCR 35h)
flashXfer.data = &configValue;
flashXfer.dataSize = 1;

status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
if (status != kStatus_Success)
{
return status;
}

//! QUAD bit set
writeValue = (configValue | FLEXSPI_CONFIG_REG_QUAD_SET_VALUE) << 8;

/* Write enable */
status = flexspi_nor_write_enable(base, 0, st_port); //!< flexspi_nor_write_enable

if (status != kStatus_Success)
{
return status;
}

/* Enable quad mode. */
flashXfer.deviceAddress = 0;
flashXfer.port = st_port;
flashXfer.cmdType = kFLEXSPI_Write;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
flashXfer.data = &writeValue;
flashXfer.dataSize = 2;

status = FLEXSPI_TransferBlocking(base, &flashXfer);
if (status != kStatus_Success)
{
return status;
}

status = flexspi_nor_wait_bus_busy(base, st_port);

/* Do software reset. */
FLEXSPI_SoftwareReset(base);

return status;
}

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 

   I mean, your DQS hardware pin, do you connect it to other module or leave it float in your hardware? As if it is not float, the flexspi communication frequency will have limit to 60Mhz.

  BTW, can you readout the CR1, whether it is confirmed the QE bit is set or not.

 

Best Regards,

kerry

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hiro33
Contributor III

Hi Kerry!

I was on summer vacation for a week, so I'm sorry for the late reply.


On my hardware, there is no DQS pin.
Is there DQS hardware pin?

I can read the CR1.

I tried running flexspi at 53MHz, but it didn't work.

Best Regards.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 

kerryzhou_0-1629178893232.png

RT1064 flexSPI contains the DQS pin, how you connect your related pins?

If you use the DQS pin, you need to set your flexSPI DQS as loopback internally, then flexSPI frequency is max 60Mhz.

Best Regards,

Kerry

 

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hiro33
Contributor III

Hi Kerry!

I'm using the DQS pin for another purpose.
I haven't set the DQS feature on the pin.
Do I also need DQS pins when using Flexspi?

Best Regards.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 

 OK, so you need to configure your used flexSPI as the looped back internally.

kerryzhou_0-1629190105821.png

And the frequency limit to 60Mhz, please add the FlexSPIn_MCR0[RXCLKSRC] =0 configration, then try it again.

Any updated information, please kindly let me know.

Best Regards,

kerry

 

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hiro33
Contributor III

Hi Kerry!

To add the FlexSPIn_MCR0[RXCLKSRC] =0 configration, I'm running the following code.

config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;

But it didn't work.

I don't have DQS pins, does the hardware still work?

The connection looks like this.

無題.png

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 , 

   You connect your QSPI on the FlexSPI B port, do you connect anything on your FlexSPI A port?

 When you read the QSPI, which address you are reading?

  What's the code you are using? 

This code?

SDK_2_10_0_EVK-MIMXRT1064\boards\evkmimxrt1064\driver_examples\flexspi\nor\polling_transfer

And modify the LUT, right?

Do you modify the pinmux.c? You need to define the FLEXSPIB port pins.

Please share your project, I need to check your code.

kerryzhou_0-1629253583757.png

Eg:

FLEXSPI_SetFlashConfig(base, &deviceconfig, kFLEXSPI_PortA1);

Do you call:

FLEXSPI_SetFlashConfig(base, &deviceconfig, kFLEXSPI_PortB1);

flexspi_nor_flash_init code:

/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
config.ahbConfig.enableAHBBufferable = true;
config.ahbConfig.enableReadAddressOpt = true;
config.ahbConfig.enableAHBCachable = true;
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;// should be kFLEXSPI_ReadSampleClkLoopbackInternally
FLEXSPI_Init(base, &config);

Just check all the related code, you need to use the B port.

Best Regards,

kerry

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hiro33
Contributor III

Hi Kerry!

>You connect your QSPI on the FlexSPI B port, do you connect anything on your FlexSPI A port?
I have nothing connected to port A.

>When you read the QSPI, which address you are reading?
I read 0x60000000.


>What's the code you are using?
>This code?
Yes.

>And modify the LUT, right?
Yes.
Please see the first post.

I upload a sample project. Please check my code.
wti_flexspi.c DbgCmdFspiReadQF1() is not work.


[Read] -> NG
SDR
cmd:0x6C Read Quad Out (4-byte Address)

[Write] -> OK
cmd:0x34 Quad Page Program (4-byte Address)

[Erase] -> OK
cmd:0xDC Erase 256 kB (4-byte address)

Best Regards.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 

  I checked your code, and find your pinmux, and the port B is correctly used.

 Now, you can do erase, write, just read can't work, please try 0XEB command to read:

/* Fast read quad mode - SDR */
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),

Which is used like the SDK code, whether this command can readout OK or not?

kerryzhou_0-1629774602987.png

Please try it and test it, then give me feedback.

Best Regards,

Kerry

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hiro33
Contributor III

Hi Kerry!

I tried 0xEB. The result went well.
Thank you for your advice!

Please tell me your way of thinking.

Why 0xEB [Quad I/O Read (3- or 4-byte address)] ?
Is it working with a 4-byte address?

Best Regards.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 ,

   Glad to hear 0xEB works on your side, our side mainly use this as the fast read in the QSPI flash.

  About 3- or 4-byte address, I think you need to check your QSPI flash chip, in my memory, some QSPI should has one bit to select 3 or 4 bytes address.

  To your chip, I think you also need to check your datasheet.

  You also can try 0XEC, this is 4 byte address.

kerryzhou_0-1629858020313.png

 

Wish it helps you!

Best Regards,

Kerry

 

 

 

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hiro33
Contributor III

Hi Kerry!

0xEC also worked fine.

Thank you for your great efforts!

Best Regards.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @hiro33 ,

   Good! Congratulations!

  Any new issues in the future, welcome to create the new case!

Best Regards,

Kerry

 

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