Receive FIFO getting filled with data from MISO line on LPSPI even though chip select signal is high

[LOKENDERVASHIST]

With IMXRT1060 LPSPI module, I am trying to send 16 bits of data during chip select PCS0 signal is low and  then once transmission is completed ,change chip select signal now to PCS1 and transmit a dummy data ( as chip select is PCS1 , slave connected with PCS0 should not respond) , disable receive interrupt and change chip select back to PCS0.

Expectation was no data should be received on MISO line when PCS0 signal is pulled high and thereby ISR should not be hit.

Problem: When PCS0 signal is pulled high then ISR is getting hit and data read is same as the data coming on MISO line , and checked status flag and found it to have receive overflow error.

 Attached code in - chip_select_change_disable_interrupt.txt

I then tried to mask the receive data using RXMSK bit and set to value of 1 so that receive data is not stored on FIFO which also didn't worked as expected and ISR got hit and read register have value same as MISO line .

Code for the above solution is at - chip_select_signal_rxmsk.txt.

Let me know how to achieve the desired results

[kerryzhou]

Hi @LOKENDERVASHIST ,

   So, your issue is mainly when the chip work as slave, right?

   And even the CS is higher, it also can receive the data, right?

   If yes, I think, it is also easy to workaround, you can check the CS pin status, if it is not 0, you can disable the receive function, then your receive FIFO won't receive the data from MISO.

Mask data also not good like to disable the RX when the CS is high.

Wish it helps you!

If you still have questions about it, please kindly let me know.

Best Regards,

kerry

[LOKENDERVASHIST]

Hello @kerryzhou 

I am using LPSI4 in master mode with PCS0(chip select 0) connected to slave and PCS1 ( chip select1) not connected. 

Issue is that when PCS0 is high , I am switching to PCS1 signal and trying to send a dummy data . At this point I am receiving data from MISO line in RXFIFO.

As PCS0 signal is high and connected to Slave , no data should be coming on MISO line from slave but its not happening and I am receiving data from MISO line.

Let me know what is the reason behind receiving data in RXFIFO when CS is logic HIGH.

[kerryzhou]

Hi @LOKENDERVASHIST ,

    Which RT chip you are using?

   In fact, sometimes, we use the GPIO as the master CS pin to control the slave.

  To the master, when you send the data MOSI, also receive the data from the MISO. even the CS is use GPIO to control, and not the IP CS function, when you do the SPI transfer, you still can receive and transfer the data.

  So, I think, that's why you also can receive the MISO data, as it don't check the CS, maybe you can consider the software method, check the CS pin level, then decide whether you need to receive the data from MISO or not.

Wish it helps you!

Best Regards,

Kerry

[LOKENDERVASHIST]

Hello @kerryzhou ,

I am using IMXRT1060 board and its LPSPI functionality.

I am not going to use CS as GPIO and rely upon IP CS function as it is our expectation to meet time constraints.

The connection between master and slave is show below for the issue described:

CS1 pin of SPI module is not connected and slave is interfaced with CS0 pin.

Below is the flow diagram for the issue:

As seen in flow diagram Receive FIFO is getting data from MISO line even though the CHIP select signal connected to slave i.e., CS0 is HIGH . As the slave is not getting CS0 signal as low it should not have sent any data to Master on MIS0 line , but observation is Receive FIFO is storing the data.

Let me know what is the reason behind the above issue and how we can disable receiving data in RXFIFO by any way in software.

Below is the signals captured  :

[kerryzhou]

Hi @LOKENDERVASHIST ,

   Thanks so much for your detailed reply, more clear than the description now.

   Please also tell me, your slave is the RT or the others?

  Now, your main issue is, to the slave, even the CS is not select, when it have clocks, and the MISO have data, the slave still receive the data.

  I am thinking, whether in your slave code, add the CS status checking, if it is not assert, you can disable the receive, just when the cs pin is enabled, it enable the receive function.

If your slave is also the RT, please tell me your used SPI Slave code, from the SDK lpspi slave?

Please tell me the slave code situation and chip, then I will help to check it.

Best Regards,

Kerry

[LOKENDERVASHIST]

Hello @kerryzhou ,

The slave is not RT it is an ADC chip : AD7689.

Further slave is connected with master with CHIP SELECT 0 signal i.e., CS0.

As shown in figure below CHIP SELECT 1 signal of LPSPI4 at master end is not connected to slave it is left unconnected:

So the main issue is at master end , as shown in the step below :

We are trying to send a dummy data from master using CS1 ( CHIP select 1) , as it is not connected to slave master should not have received any data on its MISO line as slave is not selected using CS0 as its state is high. In our case we are receiving data in RXFIFO at master end.

[kerryzhou]

Hi @LOKENDERVASHIST ,

    Thanks for your updated information.

   So, your RT as master, and change the chip select pin to the CS1 which connect to 0.

  To this situation, I think the RT receive the data is also correct, as your master LPSPI already set the chip select pin to 0, it means the LPSPI is selected, when you do the receive, it will also receive the data, even the MISO is 0. 

  If you don't need this data, I think you can do the CR[RRF]=1 to reset the receive FIFO.

Wish it helps you!

Best Regards,

kerry