MIMXRT1176CVM8A (MIMXRT1176 Family's): For possibility of using GPIO SNVS as normal GPIOs.

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

MIMXRT1176CVM8A (MIMXRT1176 Family's): For possibility of using GPIO SNVS as normal GPIOs.

Jump to solution
141 Views
Yogesh96
Contributor II

Hi Team,

We are using MIMXRT1176CVM8A in our design whose SNVS bank's GPIO are not Tamper pins. We are not connecting battery to VDD_SNVS_IN since we have separate battery backed up RTC interface to the controller.

We have connected 3.3V external supply to VDD_SNVS_IN. The output of the VDD_SNVS_ANA is 1.8V which is given to NVCC_SNVS supply. 

However, owing to GPIO shortage in our design, we are thinking of using the SNVS Bank's GPIO as normal GPIO pins. 

But if we connect the VDD_SNVS_ANA to NVCC_SNVS, then the max source/sink capability of the all the pins of SNVS bank comes to 1mA which is way below what we need.

 

Hence, we are thinking of connecting external VDD_1V8 to the NVCC_SNVS.

Can you please look into this and suggest if it can be done.? 

Our intention is to connect external 1.8V to NVCC_SNVS and make use of the SNVS Bank's GPIO to have higher current drive capability to drive the MOSFET drivers of LEDs

Tags (1)
0 Kudos
Reply
1 Solution
98 Views
Omar_Anguiano
NXP TechSupport
NXP TechSupport

The chip internal LDO VDD_SNVS_ANA should be tied together with NVCC_SNVS. I do not suggest using a configuration outside our recommendations.

Best regards,
Omar

View solution in original post

0 Kudos
Reply
1 Reply
99 Views
Omar_Anguiano
NXP TechSupport
NXP TechSupport

The chip internal LDO VDD_SNVS_ANA should be tied together with NVCC_SNVS. I do not suggest using a configuration outside our recommendations.

Best regards,
Omar

0 Kudos
Reply