IMXRT685-HIFI4 USART DMA only sent once ?

[Padi-2023]

In hifi4 interrupt, the code of CM33 is transplanted in, there is a thorny problem: uasrt0 can only be sent once using dma, and there is no usart_call_back, so the flag bit is not cleared in time, is it necessary to set USART0 interrupt in HIFI4? And how to configure XOS processes to register interrupt handlers?

[Padi-2023 · Accepted solution]

The problem has been resolved, the HIFI4 needs to register the activation interrupt mechanism.

[Gavin_Jia]

Hi @Padi-2023 ,

Hope you are doing well!

Could you help me check this AN: 8-channel DMIC Audio Acquisition on RT600 HiFi4 (nxp.com)

There are two DMA controllers in i.MX RT600. Generally, the main recommended usage method is to allocate DMA0 to CM33 and DMA1 to HiFi4. There are several points to note when using DMA in HiFi4:
• HiFi4 interrupt should be registered and enabled in XOS or XTOS. The XOS is an embedded kernel from Cadence is designed for efficient operation on embedded systems built and the XTOS is a single-threaded runtime for Xtensa processors.
• The SRAM address of DMA operation needs to be non-cacheable.
• HiFi4 interrupt needs to be configured by INPUTMUX

Best regards,

Gavin