I have two custom boards using the i.MX RT1011 MCU. Both have identical power and debug connections. One board works fine (this one has an MIMXRT1011DAE5A) and my JLink has no problem connecting. The other board (this one has an MIMXRT1011CAE4A) seems to power-up fine (all supply pins are at expected levels), but I cannot connect with the JLink debugger.
When trying to debug with MCUXpresso, I just get a message saying JLink could not connect. Using the JLink Commander, I can get some more detail. The snippet below is the output when trying to connect using JTAG:
Device "MIMXRT1011XXX4A" selected.
Connecting to target via JTAG
TotalIRLen = 5, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x088C701D, IRLen: 04, JTAG-DP
Found 1 device in JTAG chain, IRPost/DRPost != 0. Reset IRPost/DRPost to 0.
Failed to power up DAP
And in SWD mode:
J-Link>connect
Device "MIMXRT1011XXX4A" selected.
Connecting to target via SWD
Cannot connect to target.
Interestingly, when using my working board, it shows unable to connect using JTAG, but it can connect with SWD:
J-Link>connect
Device "MIMXRT1011XXX4A" selected.
Connecting to target via JTAG
TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Cannot connect to target.
SWD:
J-Link>connect
Device "MIMXRT1011XXX4A" selected.
Connecting to target via SWD
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p2, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI
ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7
ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG
Cache: Separate I- and D-cache.
I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 8 KB, 64 Sets, 32 Bytes/Line, 4-Way
Cortex-M7 identified.
The only other significant difference between these two boards is with the main 24MHz oscillator: the working board is using the standard 24MHz fundamental mode crystal connected between XTALI and XTALO, while the non-functional board uses an external oscillator feeding into XTALI with XTALO floating. The clock amplitude is as suggested in the reference manual and I do see a signal on XTALO, and I can also see the quiescent current drop significantly if I pull XTALI to GND, so I believe this is working as intended.
I'm worried this might have something to do with one of the JTAG security settings, but don't know how to check if that is the case. Is there any difference between the MIMXRT1011DAE5A and MIMXRT1011CAE4A with regards to JTAG/SWD or boot? My understanding is that the only differences between these two devices are operating temperature range and maximum frequency.
