How to recover bricked MIMXRT1015DAF5A?

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How to recover bricked MIMXRT1015DAF5A?

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audio_guy
Contributor III

I'm working on a project with a custom board and MIMXRT1015DAF5A. Several of my boards stop responding in the IDE after initially working. I'm booting mode 10b (internal) and when I try J-Link commander I get the error message:

SEGGER J-Link Commander V6.70b (Compiled Apr 3 2020 11:45:44)
DLL version V6.70b, compiled Apr 3 2020 11:44:53

Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Mar 19 2020 11:10:39
Hardware version: V10.10
S/N: 850100616
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref=3.335V


Type "connect" to establish a target connection, '?' for help
J-Link>
Unknown command. '?' for help.
J-Link>
Unknown command. '?' for help.
J-Link>connect
Please specify device / core. <Default>: MIMXRT1015DAF5A
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
T) cJTAG
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "MIMXRT1015DAF5A" selected.


Connecting to target via SWD
Found SW-DP with ID 0x0BD11477
Failed to power up DAP
Found SW-DP with ID 0x0BD11477
Failed to power up DAP
Found SW-DP with ID 0x0BD11477
Failed to power up DAP
Found SW-DP with ID 0x0BD11477
Failed to power up DAP
Cannot connect to target.
J-Link>

I think there may be some bad code in external QSPI FLASH so I switched to boot mode 01b (serial) and now the part responds by I cannot erase the FLASH:

SEGGER J-Link Commander V6.70b (Compiled Apr 3 2020 11:45:44)
DLL version V6.70b, compiled Apr 3 2020 11:44:53

Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Mar 19 2020 11:10:39
Hardware version: V10.10
S/N: 850100616
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref=3.335V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. <Default>: MIMXRT1015DAF5A
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
T) cJTAG
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "MIMXRT1015DAF5A" selected.


Connecting to target via SWD
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI
ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7
ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG
Cache: Separate I- and D-cache.
I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way
Cortex-M7 identified.
J-Link>exec enable eraseallflashbanks
ERROR: Unknown command
J-Link>exec enableeraseallflashbanks
J-Link>erase all
Erasing device...
J-Link: Flash download: Total time needed: 0.089s (Prepare: 0.057s, Compare: 0.000s, Erase: 0.031s, Program: 0.000s, Verify: 0.000s, Restore: 0.000s)

****** Error: Failed to erase sectors.

ERROR: Erase returned with error code -5.
J-Link>

Any ideas?

Peter

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audio_guy
Contributor III

I managed to get the boards back up and running. It seemed that using 10K pull-up resistors does not reliably configure the BOOT_MODE pins, 1K or 2K does. After resolving this I used the NXP MCU Boot Utility (https://github.com/JayHeng/NXP-MCUBootUtility.git) to configure the external FLASH via USB, and then erased the FLASH using JTAG using MCUXpresso IDE FLASH tool.

Thanks for the help

Peter

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audio_guy
Contributor III

My board uses LPUART1 connected to another on board device. When I connect to USB (in boot mode 01b) it does not show up as an HID device. USB sniffer shown no activity either. Is there a series of commands to erase the flash via J-Link commander?

By the way I found that the 'bad' code in FLASH is calling:

PIT_StopTimer(PIT, kPIT_Chnl_0);

when PIT is not initialized (no call to PIT_Init()). When is step into PIT_StopTimer() the jlink debugger disconnects and after this the board is bricked. I have corrected this and have a working board but would like to recover some of my other prototypes.

Finally the USB on a working board works fine running one of the evkmimxrt1015_dev_cdc_vcom_... demo projects and shows as a virtual COM port (board hardware is OK).

Peter

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jingpan
NXP TechSupport
NXP TechSupport

Hi Peter,

Before connect USB or UART port, please set the board to serial download mode. Please see table 8-2 in reference maunal.

Regards,

Jing

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audio_guy
Contributor III

I am using BOOT_MODE[1:0]=01b as stated in my post.

Peter

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

If the chip is configured to serial download mode, the application code in external memory will not be executed after reset. Please check pin setting and MCUBootUtility setting again.

Regards,

Jing

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audio_guy
Contributor III

I managed to get the boards back up and running. It seemed that using 10K pull-up resistors does not reliably configure the BOOT_MODE pins, 1K or 2K does. After resolving this I used the NXP MCU Boot Utility (https://github.com/JayHeng/NXP-MCUBootUtility.git) to configure the external FLASH via USB, and then erased the FLASH using JTAG using MCUXpresso IDE FLASH tool.

Thanks for the help

Peter

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mjbcswitzerland
Specialist V

Hi

Have you tried using NXP MCU Boot Utility to erase the SPI flash via LPUART or USB?

Regards

Mark

[uTasker project developer for Kinetis and i.MX RT]

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