Dear All,
We are using iMXRT1064 EVM board for our testing in which we are going to partition its internal SRAM from 1MB.
Below is our requirement.
SRAM_DTC: 256 KB
SRAM_OC: 768 KB
For this we changed system GPR registers to below one,
In board.c file,
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
There is no region selection for 768KB in 'ARM_MPU_RASR' register settings.
Also we have done below register settings in startup code.
"LDR R0, =0x400ac044\n"//Address of register IOMUXC_GPR_GPR17
"LDR R1, =0xAAAAAAAA\n"
"STR R1,[R0]\n"
"LDR R0,=0x400ac040\n"//Address of register IOMUXC_GPR_GPR16
"LDR R1,[R0]\n"
"ORR R1,R1,#6\n"//The 4 corresponds to setting the FLEXRAM_BANK_CFG_SEL bit in register IOMUXC_GPR_GPR16
"STR R1,[R0]\n"
"LDR R0,=0x400ac040\n"//Address of register IOMUXC_GPR_GPR16
"LDR R1,[R0]\n"
"AND R1,R1,#0xfffffffe\n"//Disabling SRAM_ITC in register IOMUXC_GPR_GPR16
"STR R1,[R0]\n"
"LDR R0, =0x400ac038\n"//Address of register IOMUXC_GPR_GPR14
"LDR R1, =0x900000\n"//New size configuration for the IOMUXC_GPR_GPR14 register
"STR R1,[R0]\n"
But still above configuration is not working for us.
After board flashing, its showing as 'Break at address "0xdeadbeee" with no debug information available, or outside of program code.'
Kindly please help us to proceed further.
Thanks & Regards.
Prashanth Kumar K
